US 4,360,742 AGranted

Synchronous binary-counter and programmable rate divider circuit

AssigneeBell Telephone Laboratories, Incorporated

InventorRonald L. Freyman

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Abstract

An MOS parallel carry synchronous binary counter/clock rate divider circuit has a chain of simultaneously clocked T flip-flop interconnected by an improved enable logic circuit having a plurality of identical carry stages each associated with a different flip-flop except the first and last flip-flop of the chain. Each carry stage has an input terminal connected to the inverted enable input of its associated flip-flop, an output terminal connected to the inverted enable input of the next flip-flop in the chain, a transmission gate transistor having a conduction channel connected in series between the input and output terminals and a gate connected to the normal output of the associated flip-flop, and a depletion mode load transistor having a conduction channel connected between a VDD power supply terminal and the output terminal and a gate connected to the output terminal. The carry stage associated with the first flip-flop comprises an inverter having an input connected to the normal output of the first flip-flop and an output connected to the inverted enable input of the second flip-flop. The clock rate division signal provided by the output of the last flip-flop in the chain can be made programmable by including a programming network in each carry stage. The programming network comprises one or more transistors having conduction channels coupled in series between the output terminal and ground and having gates responsive to control signals for forcing a logic "0" level on the output terminal.

Claims4

Dependent claims

A synchronous counter/divider circuit comprising a plurality of ordered flip-flop stages including a first, second and last stage, each flip-flop stage having output means for providing an output signal representing the logic state of the flip-flop stage and clock input means for receiving clock pulses, each flip-flop stage except the first one having enable means and being enabled to toggle when an enable signal at a logic "0" level is applied to the enable means, the first flip-flop stage being adapted to toggle;

means for applying a sequence of clock pulses to the clock input means of each flip-flop stage;
and
logic means responsive to the output signal from each flip-flop stage for providing an enable signal to the enable means of selected ones of the flip-flop stages according to a predetermined logic function,
characterized in that the logic means comprises a plurality of carry stages, a different one associated with each of the flip-flop stages except the last one, each carry stage except the one associated with the first flip-flop stage comprising:
an input terminal;
an output terminal;
load means coupled between the output terminal and a first terminal adapted to be coupled to a first source providing a potential at a logic "1" level;
and
transmission gate means consisting of a field effect transistor of a first channel conductivity type having a conduction channel coupled in series between the input terminal and the output terminal and a gate electrode coupled to the output means of the associated flip-flop stage, the field effect transistor being responsive to a logic "1" level at the gate electrode for providing a relatively low resistance path across the conduction channel, the input terminal of each carry stage except the one associated with the first flip-flop stage being coupled to the enable means of the associated flip-flop stage, the input terminal of the carry stage associated with the first flip-flop stage being coupled to a second terminal adapted to be coupled to a second source providing a potential at logic "0" level, the output terminal of each carry stage being coupled to the enable means of the succeeding flip-flop stage, and whereby each carry stage is responsive to a logic "1" level output signal from the associated flip-flop stage for passing a logic "0" level enable signal to the enable means of the succeeding flip-flop stage.

6 more elements

A synchronous counter/divider circuit comprising a plurality of ordered flip-flop stages including a first, second and last stage, each flip-flop stage having output means for providing an output signal representing the logic state of the flip-flop stage and clock input means for receiving clock pulses, each flip-flop stage except the first one having enable means and being enabled to toggle when an enable signal at a first logic level is applied to the enable means, the first flip-flop stage being adapted to toggle;

means for applying a sequence of clock pulses to the clock input means of each flip-flop stage;
and
logic means responsive to the output signal from each flip-flop stage for providing an enable signal to the enable means of selected ones of the flip-flop stages according to a predetermined logic function
characterized in that the logic means comprises a plurality of carry stages, a different one associated with each of the flip-flop stages except the last one, each carry stage except the one associated with the first flip-flop stage comprising:
an input terminal coupled to the enable means of the associated flip-flop stage;
an output terminal coupled to the enable means of the succeeding flip-flop stage;
load means coupled between the output terminal and a first terminal, the first terminal being adapted to be coupled to a first source of potential;
and
transmission gate means having a conduction path coupled in series between the input terminal and the output terminal and a control terminal for controlling the resistance of the path and coupled to the output means of the associated flip-flop stage, the carry stage associated with the first flip-flop stage comprising means for providing the output signal from the first flip-flop stage to the enable means of the second flip-flop stage and one or more of the carry stages except the one associated with the first flip-flop stage includes first logic means coupled to the output terminal of the carry stage and responsive to one or more control signals for providing the first logic level at the output terminal.

6 more elements

A synchronous counter/divider circuit comprising a plurality of ordered flip-flop stages including a first, second and last stage, each flip-flop stage having output means for providing an output signal representing the logic state of the flip-flop stage and clock input means for receiving clock pulses, each flip-flop stage except the first one having enable means and being enabled to toggle when an enable signal at a first logic level is applied to the enable means, the first flip-flop stage being adapted to toggle;

means for applying a sequence of clock pulses to the clock input means of each flip-flop stage;
and
logic means responsive to the output signal from each flip-flop stage for providing an enable signal to the enable means of selected ones of the flip-flop stages according to a predetermined logic function,
characterized in that the logic means comprises a plurality of carry stages, a different one associated with each of the flip-flop stages except the last one, each carry stage except the one associated with the first flip-flop stage comprising:
an input terminal coupled to the enable means of the associated flip-flop stage;
an output terminal coupled to the enable means of the succeeding flip-flop stage;
load means coupled between the output terminal and a first terminal, the first terminal being adapted to be coupled to a first source of potential;
and
transmission gate means having a conduction path coupled in series between the input terminal and the output terminal and a control terminal for controlling the resistance of the path and coupled to the output means of the associated flip-flop stage, the carry stage associated with the first flip-flop stage comprising means for providing the complemented output signal from the first flip-flop stage to the enable means of the second flip-flop stage, and one or more of the carry stages except the one associated with the first flip-flop stage includes first logic means coupled to the output terminal of the carry stage and responsive to one or more control signals for providing the first logic level at the output terminal.

6 more elements

Dependencies are inferred from the claim text.