Self-aligned metal process for field effect transistor integrated circuits

A method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline silicon body of an appropriate conductivity comprising:

• providing said silicon body;
• forming a first insulating layer on a major surface of said body;
• forming on said layer a polycrystalline silicon layer;
• forming openings in said polycrystalline silicon layer by reactive ion etching in the areas designated to be the PN junction regions of said integrated circuits which results in the structure having substantially horizontal surfaces and substantially vertical surfaces;
• forming the said PN junction regions of said integrated circuits using the remaining said polycrystalline silicon layer as the mask;
• forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces;
• reactive ion etching said second insulating layer to substantially remove the said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body;
• removing said first insulating layer from on top of the said areas designated to be the source/drain contacts;
• removing the remaining said polycrystalline silicon layer by etching to leave the said narrow dimensioned regions on said silicon body;
• and
• forming a conductive layer on said silicon body which has portions thereof electrically separated by said narrow dimensioned regions for contacting in self-alignment the sources, drains and forming in self-alignment the gate electrodes associated with the said source/drain regions for said integrated circuits.

A method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline silicon body of an appropriate conductivity comprising:

• providing said silicon body having a major surface with field effect transistor designated regions of said silicon exposed;
• forming on said major surface of said silicon body a doped polycrystalline silicon layer;
• forming openings in said polycrystalline silicon layer by reactive ion etching in the areas designated to be the gate regions of said field effect transistor integrated circuits which results in the structure having substantially horizontal surfaces and substantially vertical surfaces;
• forming the gate dielectric for said integrated circuits on the surface of said silicon body exposed in said openings;
• forming the PN junction elements of said integrated circuits by outdiffusing from said doped polycrystalline silicon layer;
• forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces;
• reactive ion etching said second insulating layer to substantially remove said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body;
• removing the remaining said polycrystalline silicon layer by etching to leave the said narrow dimensioned regions and said gate dielectric on said silicon body;
• and
• forming a conductive layer on said silicon body which has portions thereof electrically separated by said narrow dimensioned regions for contacting in self-alignment the said source/drain elements and forming in self-alignment the gate electrodes for said integrated circuits.

A method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions of a monocrystalline silicon body of an appropriate conductivity comprising:

• providing said silicon body having a major surface with field effect transistor designated regions of said silicon exposed;
• forming on said major surface of said silicon body a first doped polycrystalline silicon layer;
• forming openings in said polycrystalline layer by reactive ion etching in the areas designated to be the gate regions of said field effect transistor integrated circuits which results in the structure having substantially horizontal surfaces and substantially vertical surfaces;
• forming the gate dielectric for said integrated circuits on the surface of said silicon body exposed in said openings;
• forming the PN junction elements of said integrated circuits by outdiffusing from said doped polycrystalline silicon layer;
• forming an insulating layer upon the exposed surfaces of said first polycrystalline silicon layer;
• forming a second doped polycrystalline silicon layer on both said substantially horizontal surfaces and said substantially vertical surfaces;
• forming an insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces over said second polycrystalline silicon layer;
• reactive ion etching said insulating layer to substantially remove said insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body;
• removing the remaining first and second said polycrystalline silicon layers by etching to leave the said narrow dimensioned regions and said gate dielectric on said silicon body;
• and
• forming a conductive layer on said silicon body which has portions thereof electrically separated by said narrow dimensioned regions for contacting in self-alignment the said PN junction elements and forming in self-alignment the gate electrodes for said integrated circuits.

A method for forming a field effect transistor self-aligned dynamic RAM integrated circuit having a pattern of narrow dimensioned dielectric regions on a monocrystalline silicon body of an appropriate conductivity comprising:

• providing said silicon body;
• forming a first insulating layer on a major surface of said body;
• forming on said layer a polycrystalline silicon layer;
• forming a mask layer on said polycrystalline silicon layer which mask layer has openings over the areas in said major surface designated to be the drain and capacitor regions;
• forming a first blockout mask over said openings over the designated capacitor regions;
• forming openings in said polycrystalline silicon layer and said first insulating layer by reactive ion etching in the areas designated to be the drain regions of said integrated circuit which results in the structure having substantially horizontal surfaces and substantially vertical surfaces;
• forming the said drain regions in said major surface through said openings;
• removing said first blockout mask;
• providing a second blockout mask for said drain regions;
• forming additional openings in said polycrystalline silicon layer by reactive ion etching in the areas designated to be the said capacitor and defining the said gate region between one of said drain regions and one of said additional openings in said areas designated to be the said capacitor;
• removing said blockout mask;
• forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces;
• forming a third insulating layer over said second insulating layer;
• said second insulating layer being of a different composition then said third insulating layer;
• reactive ion etching said third insulating layer to substantially remove said third insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body;
• removing the second insulating layer except where it is beneath said narrow regions and the remaining said polycrystalline silicon layer by etching to leave the said narrow dimensioned regions and said gate and capacitor dielectrics on said silicon body;
• and
• forming a conductive layer on said silicon body which has portions thereof electrically separated by said narrow dimensioned regions for contacting in self-alignment the drains, and forming in self-alignment the gate electrodes and capacitor electrodes for said integrated circuit.