Method and apparatus for testing and verifying the operation of error control apparatus within a memory

A dynamic semiconductor memory system coupled to a bus for receiving memory commands, said memory system comprising:

• a dynamic memory including a number of addressable storage locations;
• error detection and correction circuit means coupled to said memory for detecting and correcting errors in the contents of the cells read out from said memory during a memory cycle of operation;
• timing means for providing sequences of timing signals for performing said memory cycle of operation;
• refresh and write control means coupled to said timing means, said refresh and write control means for periodically generating refresh command signals and generating row and column addresses for accessing different ones of said storage locations at a fast rate in response to signals from said timing means;
• rewrite control means coupled to said refresh and write control means and to said timing means, said rewrite control means including counter means operative in response to a predetermined number of said refresh command signals to condition said timing means to perform rewrite cycles of operation at a slow rate for detection and correction of a correctable error pattern by said error detection and correction means within an accessed storage location;
• and,
• diagnostic control means coupled to said bus, said error detection and correction means and to said rewrite control means, said diagnostic control means being operative in response to a predetermined type of memory command to condition said rewrite means to perform rewrite cycles of operation at said first predetermined rate enabling its rapid verification.

A memory controller coupled to a bus for receiving predetermined sequences of memory commands, certain ones of said memory commands including a diagnostic code defining a diagnostic mode of operation and a number of bits defining the type of diagnostic operation to be performed, said memory controller comprising:

• a dynamic memory including a number of memory module units, each unit having a plurality of word storage locations;
• error detection and correction circuits coupled to each of said memory module units for detecting and correcting errors in a corresponding number of word storage locations accessed from said units during a memory cycle of operation;
• timing means for providing sequences of timing signals for performing said memory cycle of operation;
• refresh and write control means coupled to said timing means, said refresh and write control means for periodically generating refresh command signals and row and column addresses at a first predetermined rate in response to signals from said timing means;
• rewrite control means coupled to said refresh and write control means and to said timing means, said rewrite control means including a counter and test mode control circuits coupled in series with said counter and to said refresh and write control means, said counter being operative in response to the occurrence of a predetermined number of said refresh command signals to condition said timing means to perform rewrite cycles of operation at a second predetermined rate which is must slower than said first predetermined rate for detection and correction of any correctable bit errors by said error detection and correction circuits in said pair of word storage locations specified by said row and column addresses;
• and,
• diagnostic mode control means coupled to said bus, said error detection and correction means and to said test mode control circuits, said diagnostic mode control means being operative in response to said predetermined sequence of commands to condition said test mode control circuits, said error detection and correction means and said rewrite control means to write predetermined test data patterns including groups of check code bits in all of said plurality of said storage locations of said units and to enable said rewrite control means to perform rewrite cycles of operation at said first predetermined rate upon said predetermined test data patterns for verifying that said rewrite control means is operating properly.