Full wave amplitude modulation detector circuit
AssigneeNational Semiconductor Corporation
InventorDon R. Sauer
Life of this patent
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Abstract
A current comparator is supplied with differential currents based upon an amplitude modulated radio frequency carrier. The comparator outputs are summed in a combining stage the output of which will contain a direct current proportional to the average carrier level and a current variation which represents the carrier modulation. The circuit provides very efficient detection of the modulated carrier.
Claims8
An amplitude modulation detector comprising:
- first and second supply terminals connectible to a source of operating power;
- a pair of circuit nodes;
- means coupled between said nodes and said first terminal for supplying differential currents to said nodes, said differential currents being related to an amplitude modulated radio frequency carrier wave;
- current mirror means having a common terminal and a pair of current terminals coupled between said nodes and said second supply terminal thereby to develop signals at said nodes related to said carrier wave;
- and
- means for combining said signals at said nodes to provide an output that is related to the modulation on said carrier wave wherein said means for combining comprises a two emitter transistor structure with said two emitters coupled to said nodes.
A detector circuit having a pair of differential input terminals for receiving a modulated radio frequency carrier wave signal and an output terminal for providing signal information related to the modulation of said carrier wave and the average value of said carrier wave, said circuit comprising:
- first and second supply terminals connectible to a source of operating power;
- first and second current nodes;
- first and second transistors of one conductibility type having their bases coupled to said differential input terminals, their emitters commonly coupled by way of current supply means to said first supply terminal and their collectors coupled respectively to said first and second nodes;
- third and fourth transistors complementary to said first and second transistors and having their emitters coupled in common to said second supply terminal, their collectors coupled to said first and second nodes respectively, and their bases coupled together;
- fifth and sixth transistors complementary to said first and second transistors and having their emitters coupled in common to said bases of said third and fourth transistors, their collectors coupled to said first supply terminal and their bases coupled respectively to said first and second nodes;
- and
- seventh and eighth transistors complementary to said first and second transistors with their emitters respectively coupled to said first and second nodes, their collectors coupled in common to said output terminal, and their bases coupled in common to a source of operating bias.
Dependencies are inferred from the claim text.