Clock pulse driver

A clock pulse driver for producing n individually enabled digital write clock pulse signals, n/2 first digital register clock pulse signals, and n/2 second digital register clock pulse signals from a system clock pulse signal where n is an even integer other than 0, said pulse signals having two values, a logical zero and a logical 1, each pulse of said pulse signals having a leading edge and a trailing edge, comprising:

• first circuit means for receiving said system clock pulse signal, a voltage reference signal, a delay write signal, a first delay register clock signal, a second delay register signal, and n write enable signals, said first circuit means producing n write clock pulse signals at a time at which the clock signal, the delay write signal and the write enable signals have predetermined logic values;
• said first circuit means producing the n/2 first register clock pulse signals at a time at which the system clock signal and the first delay register signal have predetermined logic value;
• and said first circuit means producing the n/2 second register clock pulse signals at a time at which the clock signal and the second delay register signal have predetermined logic values;
• and
• circuit means for producing a second clock pulse signal substantially in phase with the clock signal, and a plurality of delayed clock signals which are substantially 180 out of phase with the clock pulse signal, each such delayed clock signal being a delay write signal, a first delay register signal or a second delay register signal.

A current mode clock pulse driver for producing n individually enabled digital write clock pulse signals WP(1-n);

• n/2 digital register clock pulse signals RP((n/2-1)-1) from a digital clock signal $ where n is an even integer other than 0, said pulse signals having two values, a logical zero and a logical 1, each pulse of each of said signals having a leading edge and a trailing edge, comprising:
• first circuit means for receiving said clock signal $, a voltage reference signal VRef, a delay write signal DWP, a nonfunctional test signal, NFTS, a first delay register clock signal DRP(1-n/2), a second delay register signal DRP (n/2-1)-n and n write enable signals EW(1-n), said first circuit means producing said write clock pulse signals WP(1-n) at a time at which the following logic equation is satisfied:
• WP(n)=EW(n).multidot.NFTS.multidot.DWP.multidot.$
• said register clock pulse signals RP(1-n/2) at a time at which the following logic equation is satisfied:
• RP(1-n/2)=DRP(1-n/2).multidot.$
• and said register clock pulse signal RP((n/2+1)-n at a time at which the following logic equation is satisfied:
• RP((N/2+1-n)=DRP((n/2+1)-n).multidot.$;
• and
• circuit means for producing a clock pulse RP0 substantially in phase with the clock signal $ and a plurality of delayed clock signals Tp which are substantially in phase with the inverted clock pulse $ and in which p equals an integer other than zero;
• each of said delay clock signal Tp having its leading edge delayed a different period of time relative to the leading edges of the pulses of said clock signal $.