Integrated circuit having a plurality of current mode logic gates
AssigneeNippon Electric Co., Ltd.
InventorSuzuki Takamasa
Life of this patent
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Abstract
An integrated circuit employing a plurality of current mode logic gates operable with a low power consumption and at a high speed is disclosed. The integrated circuit comprises a terminal for receiving a reference signal from the outside, an input stage current mode logic gate supplied with an input signal from the outside and the reference signal, an internal reference voltage generator circuit for generating an internal reference voltage having an intermediate value of binary logic levels of the output signals of the input stage current mode logic gate, and an internal stage current mode logic gate supplied with the output signal from the input stage logic gate and the internal reference voltage.
Claims14
An integrated circuit comprising:
- an input terminal for receiving an input logic signal having a first high level and a first low level;
- a reference voltage terminal for receiving an external reference voltage generated outside the integrated circuit, said reference voltage being intermediate in value between the levels of said input signal;
- a first stage current mode logic circuit including first and second input points for generating an internal logic signal having a second high level and a second low level, the voltage difference between said second logic levels being different from the voltage levels between said first levels;
- an internal stage current mode logic circuit including first and second input points;
- an internal reference voltage generator circuit for generating an internal reference voltage having a value intermediate between the levels of said internal logic signal;
- first means for connecting said reference voltage terminal to the second input point of said first stage current mode logic circuit;
- second means for supplying the first input point of said first stage current mode logic circuit with said input signal;
- third means for supplying the second input point of said internal stage current mode logic circuit with said internal reference voltage;
- and
- fourth means for supplying the first input point of said internal stage current mode logic circuit with said internal logic signal.
An integrated circuit comprising:
- a plurality of input terminals for receiving input logic signals, each of said input logic signals having first and second logic levels;
- a first power supply terminal for receiving a first voltage;
- a second power supply terminal for receiving a second voltage;
- a reference voltage terminal for receiving an external reference voltage generated outside the integrated circuit, said external reference voltage having an intermediate value between said first and second levels of said input logic signals;
- a plurality of first stage logic gates, each including an input point, a reference point and an output point for producing logic signals having third and fourth logic levels, the voltage difference between said third and fourth logic levels being different from the voltage difference between said first and second logic levels;
- a plurality of supply means for supplying the input points of said first stage logic gates with said input logic signals;
- means for connecting said reference voltage terminal to said reference points of said first stage logic gates;
- a plurality of second stage logic gates, each including an input point receiving the internal logic signal derived from said output point of at least one of said first stage logic gates, a reference point and an output point;
- an internal reference voltage generator for generating an internal reference voltage having an intermediate value between said third and fourth logic levels;
- and
- means for supplying the reference points of said second stage logic gates with said internal reference voltage.
An integrated circuit comprising a first voltage terminal, a second voltage terminal, first and second input terminals for receiving input signals, a reference voltage terminal for receiving a reference voltage, a first transistor having a base coupled to said first input terminal, a second transistor having a base coupled to said reference voltage terminal, a first constant current source coupled between said second voltage terminal and the emitters of said first and second transistors, a first load element coupled between said first voltage terminal and a collector of said first transistor, a second load element coupled between said first voltage terminal and a collector of said second transistor, a third transistor having a base coupled to said second input terminal and a collector coupled to said first voltage terminal, a first resistor coupled between an emitter of said third transistor and said second voltage terminal, a fourth transistor having a base coupled to said reference voltage terminal and a collector coupled to said first voltage terminal, a second resistor coupled between an emitter of said fourth transistor and said second voltage terminal, an internal reference voltage generator generating an internal reference voltage having an intermediate value of binary logic levels at the collector of said first transistor, a fifth transistor having a base coupled to the collector of said first transistor, a sixth transistor having a base supplied with said internal reference voltage, a third load element coupled between a collector of said fifth transistor and said first voltage terminal, a fourth load element coupled between a collector of said sixth transistor and said first voltage terminal, a seventh transistor having a collector coupled to the collector of said fifth transistor and a base coupled to the emitter of said third transistor, an eighth transistor having a collector commonly coupled to the emitters of said fifth and sixth transistors and a base coupled to the emitter of said fourth transistor, and a second constant current source coupled between emitters of said seventh and eighth transistors and said second voltage terminal.
An integrated circuit comprising first and second input terminals for receiving input signals, a reference voltage terminal for receiving a reference voltage having an intermediate value of binary logic levels of said input signals, a first current mode logic gate performing logic operation in response to the input signal at said first input terminal and said reference voltage, a first emitter-follower transistor receiving the input signal at said second input terminal, a second emitter-follower transistor receiving said reference voltage, a reference voltage generator for generating an internal reference voltage having a substantially intermediate value of binary logic levels of the output signal of said first logic gate, and a second current mode logic gate including first pair of emitter-coupled transistors performing switching operation in response to the output signals from said first and second emitter-follower transistors and a second pair of emitter-coupled transistors whose emitters are commonly coupled to one of collectors of said first pair emitter-coupled transistors, said second emitter-coupled transistors performing switching operation in response to the output signal of said first logic gate and said internal reference voltage.
Dependencies are inferred from the claim text.