Method of checking validity of coded alpha/numeric signals with a data processor and a memory
AssigneeCompagnie Internationale pour l'Informatique Cii-Honeywell Bull
InventorJacques Sery
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AssigneeCompagnie Internationale pour l'Informatique Cii-Honeywell Bull
InventorJacques Sery
Estimating the term…
The validity of a code, such as an alpha-numeric code, constituted by a series of elements and including a checking key corresponding to the digit value of the first element of the code, is checked by a memory including an addressable dual-input table having a number of rows at least equal to the maximum number of elements of the code and a number of columns at least equal to all the possible numerical values of the code element. Columns and rows of the table are respectively addressed by the numerical value of a code element and by the relative position of the code elements in the code. The location defined by the intersection of the addressed column and row contains an entry for a remainder resulting from division by a given modulus of the numerical value of the code element multiplied by a coefficient assigned to the position. Each element of the code and the corresponding remainder contained in the location of the memory addressed by the code element are read by a processing means. The processing means adds the read remainder to a previous remainder and divides the sum of the addition operation by the modulus to obtain a new remainder. The checking key associated with each code is stored in the first row of the table. The checking key or first remainder are such that the final remainder obtained for the last element of the code is equal to zero when the code is correctly read.
A method of checking the validity of coded signals adapted to represent alpha and numerical values, each of said coded signals consisting of (a) a series of code elements and (b) a checking key corresponding to a digit value of a first element of the coded signals, the coded signal being checked with a data processing means and a memory including an addressable dual input table having a number of rows at least equal to the maximum number of code elements of each coded signal and a number of columns at least equal to all the possible numerical values of a code element, columns and rows in said table being respectively addressed by the numerical value of a code element and by the relative position of said code element in the coded signal, the location defined by the intersection of the addressed column and said row containing an entry for a remainder, the remainder having a value equal to the numerical value of said code element multiplied by a coefficient assigned to the relative position divided by a given modulus, comprising the steps of, in the data processing means:
Dependencies are inferred from the claim text.