Dual function ECC system with block check byte
AssigneeInternational Business Machines Corporation
InventorArvind M. Patel
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AssigneeInternational Business Machines Corporation
InventorArvind M. Patel
Estimating the term…
An improved ECC method and system are disclosed for correcting either a random single-bit error, or alternately, a multi-bit error in one byte of a data word from a single syndrome byte. The improvement involves determining the location of the multi-bit error in successive data words which result because of a failure in one of a plurality of failure independent storage units employed for storing a block of multi-byte words. The location of the defective byte position is determined by summing each non-zero syndrome byte that is developed for each multi-byte word that is processed to produce a summed syndrome byte .SIGMA.S.noteq.0. This summed syndrome byte is then employed to generate a set of vectors which are positionally related in an m-sequence to the summed syndrome byte. A block syndrome byte, developed during the processing of a number of words and representing the sum modulo-2 of the error pattern in each word of the block, is compared to each of the set of vectors. The position of the vector relative to the summed syndrome byte compared to the block syndrome byte then provides an indication of the byte position in each word which is in error. With the defective byte position identified, the individual syndrome bytes for each word are then employed to develop for each word the correct error pattern for the defective byte position of each word.
In a dual function ECC system for alternately correcting from a single syndrome byte random 1-bit errors in a data word having M-1 data byte positions and one check byte position, or multi-bit errors in the same byte position of successive data words, where corresponding bytes of successive data words are each stored in a failure independent storage unit and where each said syndrome byte is developed from a write check character and a read check character where each bit position of said check characters represents the modulo-2 sum of the value of data in bit positions of a data word which have been selected from a parity check matrix H' derived from a parity check matrix H which corresponds to an m-sequence of length 2.sup.b -1 where b is equal to the number of bit positions in each said byte, said H' matrix being derived by selecting M b.times.b submatrices from said H matrix which are spaced apart .lambda.-b columns, where .lambda. is greater than b and is selected such that none of the selected submatrices overlap, and means for generating said syndrome byte for each word, said system including:
In a method for processing a b bit syndrome byte where said syndrome byte is one of M vectors which are positionally related in an m-sequence of length 2.sup.b -1 to alternately correct a random single-bit error in one of M byte positions of data word or a multi-bit error in the same byte position of successive said words, and where each non-zero syndrome byte is processed to determine the byte location of a single-bit error and the single-bit error pattern, the improvement comprising the steps of:
A dual function ECC system having a write check character generator, a read check character generator, a syndrome generator responsive to the output of said check generators, and a syndrome processing circuit for correcting a single random 1-bit error in each multi-byte data word for which said syndrome generator produces a non-zero syndrome byte characterized by:
Dependencies are inferred from the claim text.