US 4,358,847 A · Electrical circuit test apparatus and method

Abstract

An electrical circuit test apparatus and method are disclosed for detecting faults in n-input combinational circuitry. The testing is performed by the verification of the Walsh coefficients. This is an alternative to the usual Boolean based techniques. To implement the Walsh coefficient verification, a reversible counter is utilized in conjunction with a driving counter, a parity indicating means, and minor control circuitry. The output signal from the unit under test is compared with the parity signal derived from the driving counter, and where there is correspondence, the reversible counter is actuated in one direction. Where they are dissimilar, the reversible counter counts in the opposite direction. A circuit is considered faulty where the final indication in the reversible counter is zero. It has been found that the Walsh spectrum of any given combination logic function f(x) of n independent variables x.sub.1 to x.sub.n consists of a series of 2.sup.n integer numbers, the magnitude and sign of which constitute the spectral coefficient values of f(x). Therefore, because the spectral coefficient values define the output function uniquely, the values for a network with an output fault will differ from these without fault.

Claims8

Dependent claims

Apparatus for testing an n-input combinational circuit comprising

(a) an input signal pattern means for generating a plurality of electrical input signal patterns, said plurality consisting of the set of all binary numbers that can be formed from n digits, said means adapted to address each of said signal patterns sequentially to the input leads of a circuit to be tested,
(b) a parity signal generating means for emitting a parity signal responsive to each input signal pattern generated by said input signal means, said parity signal being 0 to 1 and being indicative of whether the number of zeros in each of said input signal patterns is odd or even,
(c) reversible counter means adapted to receive from a circuit under test, an output signal either 0 or 1 for each input signal pattern addressed thereto and comparing the corresponding parity signal therewith, said reversible counter means including arithmetic scoring means for cumulatively either
(1) if said parity signal is one for an even number of zeros in an input signal pattern, adding a one each time said output signal and parity signal are the same, subtracting a one each time they are different, or
(2) if said parity signal is 0 for an even number of zeros in an output signal pattern, adding a one each time said output signal and parity signal are different and substracting a one each time they are the same.

2 more elements

Dependencies are inferred from the claim text.

Electrical circuit test apparatus and method

Life of this patent

Electrical circuit test apparatus and method

Life of this patent

Abstract

Claims8