Self-biasing circuit for analog shift registers, with fat zero compensation

A storage system comprising:

• a series shift register array composed of a plurality of capacitance charge transfer cells serially arranged between an input terminal and an output terminal, each cell storing a single bit of information and consisting of only a transistor having input, output, and control terminals and a storage capacitor connected between the output terminal of the transistor and its control terminal,
• an input stage coupled to the input terminal of said series shift register,
• an output stage coupled to the output terminal of said series shift register,
• first voltage means coupled to the control terminals of alternate cells in the series for introducing into the storage system a first sequence of pulses to cause the information in said alternate cells to be sequentially transferred to cells positioned adjacent said alternate cells, and
• second voltage means coupled to the control terminals of said adjacent cells for intorducing into the storage system a second sequence of pulses to cause the information in said adjacent cells to be sequentially transferred into said alternate cells,
• said input stage including a fat zero charge generator comprising a capacitively loaded semiconductor device.

A storage system comprising:

• a series shift register array composed of a plurality of capacitive charge transfer cells serially arranged between an input terminal and an output terminal, each cell storing a single bit of information and consisting of only a transistor having input, output, and control terminals and a storage capacitor connected between the output terminal of the transistor and its control terminal,
• an input stage coupled to the input terminal of said series shift register,
• an output stage coupled to the output terminal of said series shift register,
• first voltage means coupled to the control terminals of alternate cells in the series for introducing into the storage system a first sequence of pulses to cause the information in said alternate cells to be sequentially transferred to cells positioned adjacent said alternate cells, and
• second voltage means coupled to the control terminals of said adjacent cells for introducing into the storage system a second sequence of pulses to cause the information in said adjacent cells to be sequentially transferred into said alternate cells,
• said input stage including a first voltage node,
• a source of reference potential,
• first capacitance means connected to said first voltage node,
• means for periodically electrically coupling said source of reference potential to said first voltage node and said first capacitance means to charge said first capacitance means to a selected potential
• a second voltage node,
• a second capacitor, coupled to said second voltage node, and
• a semiconductor diode coupled between said first and said second voltage node for charging said second voltage node to a level determined by said selected potential and the characteristic of said diode.

A fat zero charge generator for a charge-transfer device, comprising:

• a voltage node;
• a source of reference potential;
• capacitance means connected to said voltage node;
• means for periodically electrically coupling said voltage node to said charge-transfer device to provide transfer of a predetermined quantity of charge between said voltage node and said charge-transfer device representative of a minimum transferable charge;
• and
• diode-connected semiconductor means coupled to said voltage node for predischarging said capacitance means to within one diode voltage drop of said reference potential during a time other than when said voltage node is coupled to said charge-transfer device.