Digital voltage comparator
AssigneeTeletype Corporation
InventorGary B. Ollendick
Life of this patent
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Abstract
A digital voltage comparator is illustrated including a cross-coupled latch 10 having input nodes 12 and 14. After the input nodes 12 and 14 of the latch 10 have been respectively preloaded to the input A and reference E voltage levels during the active state of clock phase .phi..sub.1, the latch is allowed to arrive at a stable state during the active state of clock phase .phi..sub.2. Thereafter, when clock phase .phi..sub.3 is active, the output of the latch 10 is coupled to the input of a single stage shift register 20. The output of the shift register 20 is fed to inverters 22 and 26 and through a voltage divider for preloading the node 14 of the latch 10 during the next active state of clock phase .phi..sub.1.
Claims7
A digital voltage comparator for comparing an input signal (A) with a reference voltage (E) comprising:
- a bistable latch (10) having first and second nodes (12, 14),
- first means (36) for preloading said first node (12) to a voltage level determined by the input signal (A),
- second means (70) for preloading said second node (14) to voltage level (C) determined by the reference voltage (E),
- third means (46) for subsequently allowing the latch (10) to race to a stable state as determined by the voltage levels (B, C) of said nodes (12, 14),
- fourth means (20) for storing a signal level (D) related to the stable state of said latch (10),
- fifth means (26) responsive to the signal level (D) of said fourth means (20) for providing said reference voltage (E) to said second means (70) during preloading of said latch (10) subsequent to the storing of the signal level (D) related to the stable state of said latch (10) by said fourth means (20),
- sixth means (22) for providing an output signal (F) which is related to a stable state of said latch (10), said sixth means (22) provides an output signal (F) from the storage means (20) which is related to the input signal (A) to the latch (10) during a preceding time period,
- a system clock (18) having a plurality of clock phases (.phi..sub.1, .phi..sub.2, .phi..sub.3),
- said first and second means (36, 70), being controlled by a first clock phase (.phi..sub.1) of said system clock (18),
- said third means (46) being controlled by a second clock phase (.phi..sub.2) of said system clock (18), and
- said fourth means (20) being controlled by said first and a third clock phase (.phi..sub.1, .phi..sub.3) of said system clock (18).
A digital voltage comparator for comparing an input signal (A) with a reference voltage (E) comprising:
- a bistable latch (10) having first and second nodes (12, 14),
- first means (36) for preloading said first node (12) to a voltage level determined by the input signal (A),
- second means (70) for preloading said second node (14) to voltage level (C) determined by the reference voltage (E),
- third means (46) for subsequently allowing the latch (10) to race to a stable state as determined by the preloaded voltage levels (B, C) of said nodes (12, 14),
- fourth means (20) for storing a signal level (D) related to the stable state of said latch (10),
- fifth means (26) responsive to the signal level (D) of said fourth means (20) for providing said reference voltage (E) to said second means (70) during preloading of said latch (10) subsequent to the storing of the signal level (D) related to the stable state of said latch (10) by said fourth means (20),
- sixth means (22) for providing an output signal (F) which is related to a stable state of said latch (10),
- a system clock (18) having a plurality of clock phases (.phi..sub.1, .phi..sub.2 and .phi..sub.3),
- said first and second means (36, 70), being controlled by a first clock phase (.phi..sub.1) of said system clock (37),
- said third means (46) being controlled by a second clock phase (.phi..sub.2) of said system clock (18), and
- said fourth means (20) being controlled by said first (.phi..sub.1) and said third (.phi..sub.3) clock phases of said system clock (18).
Dependencies are inferred from the claim text.