Digital phase lock loop for flexible disk data recovery system
AssigneePertec Computer Corporation
InventorDale E. Delury
Life of this patent
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AssigneePertec Computer Corporation
InventorDale E. Delury
Estimating the term…
A digital phase lock loop system used in conjunction with a flexible disk drive controller for recovering data information from either single density or double density serially encoded data. More specifically, a phase lock system is disclosed in which data bit windows and clock bit windows are defined by a plurality of phase clock cycles. A circuit is provided for determining during which phase clock cycle a bit occurs, an adjustment being made to the duration of its corresponding bit window and thus to the initiation time of a subsequent bit window which will tend to position the window so that it will be centered about its corresponding bit. In a specific embodiment for double density encoded data, a circuit is provided whereby the subsequent bit window is positioned in accordance with the position of the current bit within its corresponding window and the position of a preceding bit within its corresponding bit window. In addition, the invention provides a circuit whereby a position of each bit within its corresponding window is counted, the net count being indicative of the number of bits appearing in the second half of their corresponding bit windows less the number of bits appearing in the first half of their corresponding bit windows. A bias phase adjustment signal is generated for altering the duration of a bit window until the net count approaches zero. This altering provides for automatic compensation of variations in disk rotation speed and/or recording speed variations.
A system for generating a signal in phase lock with data bits within an encoded bit stream having data bits and clock bits, comprising:
In combination with a flexible disk data recovery system wherein an encoded bit stream having data bits and clock bits is obtained from a flexible disk, a means for generating a signal in phase lock with said data bits, comprising:
A system for generating a signal in phase lock with data bits within an encoded bit stream having data bits and clock bits comprising:
A method of generating a signal in phase lock with bits within an encoded bit stream having data bits and clock bits, comprising the steps of:
In combination with a data source providing a stream of bits, means for generating a signal comprised of bit windows occurring in synchronism with said bits, said signal generating means comprising:
In a system for obtaining data bits from an encoded bit stream containing data bits and clock bits, the improvement comprising:
Dependencies are inferred from the claim text.