US 4,357,674 A · PCM Signal calculator

Abstract

A PCM signal calculator for non-linear encoded PCM signals in the A-law system or .mu.-law system having a sign bit and a plurality of absolute value bits with three bits of segment number and four bits of step numbers within segment comprises; (a) a pair of input terminals for receiving the input PCM signals; (b) a signal or plurality of calculation means for providing the addition, subtraction and/or multiplication between the absolute values of two input PCM signals; (c) means for providing sign bit of the calculated result from the sign bits of the input PCM signals and/or the output of said calculation means; (d) an output terminal for providing the sign bit of the result from said means (c) and the absolute value of the result from said means (d). Said calculation means is either a table memory storing the result of each calculation according to the address designated by the input signals or combination of electronic components operating input PCM signals with segment number and step number within segment like a floating point number. Thus, the calculation of PCM signals encoded with non-linear encoding system like A-law and/or .mu.-law is performed without converting the PCM signals to linear signals.

Claims8

Dependent claims

A PCM signal calculator for addition of two input PCM signals P and Q each having a sign bit and a plurality of absolute value bits encoded to non-linear encoding system selected from A-law encoding system and .mu.-law encoding system with segment number and step number within segment comprising:

(a) a pair of input terminals for receiving two input PCM signals P and Q, each including a predetermined sign bit;
(b) first calculation means coupled to said input terminals responsive to PCM signals for providing an output equivalent to the sum of the absolute values of said two input PCM signals;
(c) second calculation means coupled to said input terminals responsive to PCM signals for providing an output equivalent to the difference between the absolute values of said two input PCM signals;
(d) an OR-gate coupled to and receiving the outputs of said means (b) and (c);
(e) means for applying the output of said first calculation means (b) to said OR-gate when the said sign bits of said two input PCM signals P and Q are the same as each other, and the output of said second calculation means (c) to said OR-gate when the said sign bits of said two input PCM signals P and Q are different from each other;
(f) a combination logic circuit for providing the sign bit of the sum of said two input PCM signals P and Q by providing the sign bit of either one of said two input PCM signals when the said sign bits of said input PCM signals P and Q are the same as each other, and by providing the combination logic result of the said sign bits of said two input PCM signals and said sign bit included in the output of said second calculation means (c) when the said sign bits of said input PCM signals P and Q are different from each other;
and
(g) output terminal for providing the absolute value from the output of said OR-gate, and the sign bit from the output of said combination logic circuit.

5 more elements

Dependencies are inferred from the claim text.

PCM Signal calculator

Life of this patent

PCM Signal calculator

Life of this patent

Abstract

Claims8