Method and apparatus for disabling and diagnosing cache memory storage locations

In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, each storage location identified by an index address, said cache memory capable of comparing signals representative of an address of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, a method for diagnosing the operation of addressable cache memory storage locations comprising the steps of:

• (a) intentionally disabling predetermined ones of said plurality of addressable cache memory storage locations, leaving remaining addressable cache memory storage locations desired to be diagnosed by an operator of the data processing system enabled;
• (b) creating diagnostic program instructions capable of being executed by said processor and having index addresses identifying said addressable cache memory storage locations desired to be diagnosed;
• (c) loading said diagnostic program instructions into ones of said plurality of addressable main memory storage locations by by-passing said disabled predetermined ones of said plurality of addressable cache memory storage locations;
• and
• (d) testing said enabled locations of said addressable cache memory storage locations by executing said diagnostic program instructions stored in said addressable plurality of main memory storage locations.

In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, said cache memory also having hit/miss logic circuitry capable of comparing signals representative of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, cache control logic means for disabling predetermined ones of said plurality of addressable cache memory storage locations comprising:

• (a) means to generate signals representative of the predetermined ones of said plurality of addressable cache memory storage locations intentionally desired to be disabled by an operator of the data processing system;
• and
• (b) signal comparison means, receptive of said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations and signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction, coupled to said cache memory hit/miss logic circuitry and capable of developing an output signal which causes said data processing system to access said addressable main memory storage location being addressed when said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations are in a predetermined fixed relationship with said signals representative of the addressable main memory storage location being addressed by the processor during the execution of a program instruction.