Annealing of ion-implanted GaAs and InP semiconductors
AssigneeThe United States of America as represented by the Secretary of the Navy
InventorBela Molnar
Life of this patent
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Abstract
A method of annealing both N and P-type ion-implanted GaAs and InP semiconductors by using a close-contact capping technique. A flat polished ion-implanted surface on a gallium arsenide (GaAs) or indium phosphide (InP) semiconductor is placed in face-to-face contact with a non-reactive flat surface such as Si.sub.3 N.sub.4, SiO.sub.2, AlN, or identical semiconductor material, and annealed at selected elevated temperatures and time dependent upon ion concentration. The annealed semiconductor material, usually in the form of a wafer, is allowed to cool to room temperature for further processing.
Claims8
A process of annealing ion-implanted semiconductor material comprising the steps of:
- selecting an unannealed semiconductor material having an ion-implanted polished surface;
- selecting a like semiconductor material having a polished surface larger than that of the first-mentioned surface;
- positioning the unannealed semiconductor material in surface-to-surface contact with the larger surface which extends beyond the periphery of the smaller surface;
- maintaining the surfaces in contact;
- and
- annealing the ion-implanted semiconductor material substantially in the absence of oxygen whereby evaporation of material from the implanted surface is minimized.
A process of annealing an ion-implanted semiconductor material comprising:
- selecting an unannealed semiconductor material from the group consisting of GaAs and InP having a polished surface implanted with ions selected from the group consisting of Be.sup.+, 29Si.sup.+ and Se.sup.+ ;
- selecting a like semiconductor material having a surface area greater than the area of the ion-implanted surface and provided with a coating of dielectric material on the surface selected from the group consisting of Si.sub.3 N.sub.4, SiO.sub.2 and AlN polished to a smoothness substantially matching that of the first mentioned surface;
- positioning the surfaces in face-to-face contact with peripherial portions of the larger surface surrounding the, smaller surface;
- maintaining the surfaces in contact;
- and
- annealing the ion-implanted semiconductor material in an atmosphere of nitrogen and hydrogen whereby evaporation of material from the implanted surface is minimized.
A process of annealing a wafer of ion-implanted semiconductor material comprising the steps of:
- selecting an unannealed semiconductor wafer selected from the group consisting of GaAs and InP having a polished planar surface implanted with ions selected from the group consisting of Be.sup.+, 29Si.sup.+ and Se.sup.+ ;
- coating a Si matrix with a layer of dielectric material selected from the group consisting of Si.sub.3 N.sub.4, SiO.sub.2 and AlN;
- providing a polished planar surface on the dielectric material having an area larger than the area of the planar surface on the semiconductor wafer;
- positioning the polished surfaces together in face-to-face contact with excess area of the larger planar surface extending beyond the outer periphery of the smaller planar surface;
- maintaining the surfaces in face-to-face contact;
- planning the positioned materials into a container;
- purging the container to have an embient environment gas of approximately 15% H.sub.2 and 85% N.sub.2 ;
- placing the container in a furnace at an elevated temperature for a predetermined time;
- removing the container from the furnace and allowing the materials to cool to substantially room temperature;
- changing the ambient gas to N.sub.2 ;
- and
- removing the annealed semiconductor.
Dependencies are inferred from the claim text.