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US 4,356,460 AGranted
Split phase delay equalizer with reduced insertion loss
AssigneeRockwell International Corporation
InventorVernon R. Cunningham
Life of this patent
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Abstract
A split phase delay equalizer is provided which reduces loss without resorting to high values of load impedance. The equalizer has a pair of parallel circuit branches, one of which is through the base and collector of a transistor, and the other through a reactance network connected between the collector and base of the transistor.
Claims7
A split phase delay equalizer using a single transistor which has a transfer function complying with the Equation ##EQU19## where R is a transistor gain stabilizing resistor as referenced infra, where RL is the load resistance seen by the equalizer,
- where RG is the signal source resistance seen by the equalizer, and
- where X is the impedance of a circuit branch as referenced infra, comprising, in combination:
- a pair of circuit branches connected in parallel between an input and an output;
- a transistor in one of said pair of circuit branches for providing a 180 degree phase inversion of the signal in that branch;
- reactance means X in the other one of said pair of circuit branches for providing a phase shift of the signal in that branch;
- a resistance means R connected in circuit with the transistor in said one of said pair of circuit branches, said equalizer receiving signals from a generator having an impedance of RG and connected to supply signals to a load having a resistance value RL;
- and
- means connecting the base of said transistor to said input and connecting one of the emitter and collector of said transistor to the output, wherein said reactance means is connected in feedback relation from said one of the emitter and collector of said transistor to the base of said transistor.
5 more elements
Dependencies are inferred from the claim text.