Flexible processor on a single semiconductor substrate using a plurality of arrays

A processor fabricated on a single semiconductor substrate comprising:

• AND array means for receiving program instructions from input sources external of the processor and for generating product signals;
• OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals;
• register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor;
• arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data;
• control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means;
• and
• multiplexer means interconnected to said register means and to data sources external of the processor for controlling flow of data to said register means under control of ones of said plurality of control signals.

A processor fabricated on a single semiconductor substrate comprising:

• AND array means for receiving program instructions from input sources external of the processor and for generating product signals;
• OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals;
• register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor;
• arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data;
• control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means;
• and
• code register means interconnected to said arithmetic and logic unit means for storing condition code information generated by said arithmetic and logic unit means for application to said AND array means.

A processor fabricated on a single semiconductor substrate comprising:

• AND array means for receiving program instructions from input sources external of the processor and for generating product signals;
• OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals;
• register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor;
• arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data;
• control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means;
• and
• wherein ones of said plurality of control signals are connected from said OR array means to input/output devices external of the processor.

A processor fabricated on a single semiconductor substrate comprising:

• AND array means for receiving program instructions from input sources external of the processor and for generating product signals;
• OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals;
• register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor;
• arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data;
• control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means;
• and
• said arithmetic and logic unit means comprises programmable logic array means.

A processor comprising:

• AND array means for receiving program instructions, clock pulses and interrupt signals from input sources external of the processor and for generating product signals;
• OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals;
• register array means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor;
• arithmetic and logic unit array means interconnected to said register array means and said OR array means for executing operations on data received from said register array means in accordance with ones of said plurality of control signals for generating output data;
• control register array means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means;
• output register array means interconnected to receive said output data and ones of said plurality of control signals for buffering said output data between said arithmetic and logic unit array means and data sources external of the processor under control of ones of said plurality of control signals;
• multiplexer register array means interconnected to said register array means and to data sources external of the processor for controlling flow of data to said register array means under control of ones of said plurality of control signals;
• code register array means interconnected to said arithmetic and logic unit array means for storing code condition information generated by said arithmetic and logic unit array means for application to said AND array means;
• and
• all said array means being fabricated on a single semiconductor substrate.

A processor fabricated on a single semiconductor substrate comprising:

• AND array means for receiving input signals from sources external of the processor and for generating outputs along product signal lines;
• OR array means disposed adjacent to said AND array means on the semiconductor substrate and interconnected to said product lines for generating control signals along control lines disposed perpendicular to said product lines;
• register array means disposed adjacent to said OR array means on the semiconductor substrate for receiving said control signals and for generating data along register signal lines;
• said register signal lines being disposed perpendicular to said control signal lines;
• arithmetic and logic unit array means disposed adjacent said register array means and said AND array means for receiving said data from said register array means along said register signal lines for generating output data;
• control register means interconnected to said OR array means and said AND array means for receiving said control signals;
• and
• output register means interconnected to receive said output data from said arithmetic and logic unit array means and said control signals for buffering said output data between said arithmetic and logic unit array means and data sources external of the processor under control of said control signals.

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising:

• AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate;
• said means external to said substrate for applying said coded input signal including clock means;
• OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths;
• register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths;
• and
• output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths.

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising:

• AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate;
• OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths;
• register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths;
• output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths;
• and
• said output means is structured as an array.

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising:

• AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate;
• OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths;
• register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths;
• output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths;
• and
• controller means, positioned on said substrate to be connected to at least a third portion of said control signal conduction paths, for providing signals to control the code of the product signals provided by said AND array means in accordance with the state of said control signal on said third portion of said control signal conduction paths, said controller means signals being provided along conductive paths positioned between said controller means and said AND array means along a path substantially perpendicular to said product signal conduction paths.

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising:

• AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate;
• OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths;
• register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths;
• output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths;
• and
• said output means includes multiplexer means.