Switched-capacitor filter circuit having at least one simulated inductance having controlled switches, capacitors, and an amplifier

In a switched-capacitor filter circuit which may be adapted to simulate a single-sided inductor or a parallel resonance circuit having a resonance frequency greater than one-sixth of the filter circuit sampling frequency or a parallel resonance circuit having a resonance frequency which is less than said sampling frequency, said filter circuit having an operational amplifier with a feedback capacitor interconnected between an output and an inverting input thereof, said amplifier also having a non-inverting input connected to a reference potential, said filter circuit operated by first, second, third, and fourth cyclically sequential clock phases having non-overlapping duty times and identical periods, and said filter circuit further having first and second input terminals, the improvement comprising:

• a first switch which is closed during said second clock phase and which is interconnected between the inverting input of said amplifier and a first circuit node;
• a first capacitor interconnected between said first circuit node and said second input terminal and the reference potential;
• a second switch which is closed during said fourth clock phase and which is interconnected between said first circuit node and a second circuit node;
• a second capacitor interconnected between said second circuit node and the reference potential;
• a third switch which is closed during said first clock phase and which is interconnected between the output of said operational amplifier and said second circuit node;
• a fourth switch which is closed during said third clock phase if said filter circuit is to simulate a single-sided inductor or a parallel resonance circuit having a resonance frequency which is less than one-sixth of said sampling frequency, said fourth switch otherwise always remaining open, said fourth switch being interconnected between the output of said operational amplifier and said first circuit node;
• and
• a fifth switch which is closed during said first clock phase and which is interconnected between the first input terminal and said first circuit node.