# US 4,353,777 A · Selective plasma polysilicon etching

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 4,353,777 A
- Document ID: US4353777A
- Status: Granted
- Kind: A
- Application number: 06/255,495
- Filed: 1981-04-20
- Granted: 1982-10-12
- Earliest claimed: 1981-04-20
- Assignees: LFE Corporation
- Inventors: Adir Jacob
- Web page: https://patentgrep.com/patent/US4353777A

## CPC

- H10P 50/268: {of silicon-containing layers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A process for etching polysilicon material preferentially over silicon oxide. The process is anisotropic and employs a moderate to low pressure of Freon 11 (CFCl.sub.3) in an RF plasma discharge. In a second embodiment helium is mixed with the Freon 11 to inhibit degradation of the photoresist mask.

## Claims

### Claim 1

Process for selectively etching polysilicon material comprising the steps of:
(a) placing polysilicon material within a reactor chamber, and
(b) exposing said polysilicon material within the chamber to a gas plasma at a pressure between 50 and 150 microns Hg for etching, wherein said gas plasma consists essentially of RF discharge CFCl.sub.3.

### Claim 2 (depends on 1)

A process in accordance with claim 1 wherein said polysilicon material is a polysilicon layer over silicon oxide.

### Claim 3 (depends on 1)

A process in accordance with claim 1 wherein power is supplied to said gas plasma at a rate between 0.2 and 2 watts per centimeter squared of power density.

### Claim 4 (depends on 1)

A process in accordance with claim 1 wherein a carrier gas of helium is added to the etchant gas.

### Claim 5

A process for fabrication of a semiconductor device having a polysilicon layer and a silicon oxide layer including the step of preferential etching of said polysilicon layer, where said preferential etching of said polysilicon layer comprises the steps of,
(a) placing said semiconductor device within a reactor chamber,
(b) exposing said semiconductor device within said reaction chamber to etchant gas consisting essentially of CFCl.sub.3 at a pressure between 50 and 150 microns Hg.

### Claim 6 (depends on 5)

A process in accordance with claim 5 wherein said polysilicon layer is to be etched with a line pattern characterized by widths of less than 4 microns and wherein said plasma is supplied power at a rate of between 0.2 and 2 watts per centimeter square of power density.