US 4,353,044 AGranted

Switched-capacitor filter circuit having at least one simulated inductor and having a resonance frequency which is one-sixth of the sampling frequency

AssigneeSiemens Aktiengesellschaft

InventorJosef Nossek

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Abstract

A switched-capacitor filter circuit having at least one simulated inductor and having a resonance frequency which is one-sixth of the sampling frequency as pulse-controlled switches co-operatively operable for connecting a first capacitor to a pair of input terminals during a first clock phase and simultaneously connecting a second capacitor to the output of an inverting integration circuit, followed by discharge of the first capacitor to a capacitor in the integration circuit during a second clock pulse phase, followed by a third clock pulse phase during which the first capacitor is charged from the output of the integration circuit and the second capacitor is simultaneously connected to the pair of input terminals and during a fourth clock pulse phase the second capacitor discharges to the capacitor in the integration circuit.

Claims14

Dependent claims

A switched-capacitor filter circuit having at least one simulated inductance, said filter circuit operating as the equivalent of a parallel resonance circuit having an inductance L and a capacitance C and having a resonance frequency which is one-sixth of the sampling frequency for the circuit, said circuit comprising:

first and second input terminals;
a first capacitor;
a means for connecting said first capacitor across said input terminals during a first clock phase;
a second capacitor;
an inverting integration circuit having a feedback capacitor and having an output;
a means for connecting said second capacitor to the output of said inverting integration circuit during said first clock phase;
a means for transferring a charge from said first capacitor to aid feedback capacitor during a second clock phase;
a means for charging said first capacitor by the output of the integration circuit during a third clock phase;
a means for connecting said second capacitor across said input terminals during said third clock phase;
and
a means for transferring a charge from said second capacitor to said feedback capacitor during a fourth clock phase, said first, second, third and fourth clock phases operating in cyclical fashion with non-overlapping duty times at the same clock frequency.

8 more elements

first and second input terminals;
a first capacitor interconnected between first and third circuit nodes;
a second capacitor interconected between second and fourth circuit nodes;
at least one additional capacitor interconnected between fifth and sixth circuit nodes;
an inverting integration circuit including an operational amplifier having inverting and non-inverting inputs and an output, a feedback capacitor interconnected between the output and the inverting input of the amplifier, said output of said amplifier serving as the output of said integration circuit and the inverting input of said amplifier serving as the input for said integration circuit, and said non-inverting input being connected to a reference potential;
a first switch interconnected between said first node and said first input terminal;
a second switch interconnected between said second node and said first input terminal;
a third switch interconnected between the output of said integration circuit and said first node;
a fourth switch interconnected between the output of said integration circuit and the second node;
a fifth switch interconnected between the input of said integration circuit and said first node;
a sixth switch interconnected between the input of said integration circuit and said second node;
a seventh switch interconnected between said second input terminal and said fourth node;
an eighth switch interconnected between said second input terminal and said third node;
a ninth switch interconnected between said fourth node and said reference potential;
a tenth switch interconnected between said third node and said reference potential;
an eleventh switch interconnected between said first input terminal and said fifth node;
a twelfth switch interconnected between said fifth node and said input of said integration circuit;
a thirteenth switch interconnected between the second input terminal and said sixth node;
a fourteenth switch interconected between said sixth node and said reference potential;
and
a fifteenth switch interconnected between said fifth node and the output of said integration circuit, said first, fourth, eighth, and twelfth switches being closed during a first clock phase, said second, fifth, seventh, and fifteenth switches being closed during a second clock phase, said third, sixth, eleventh, and thirteenth switches being closed during a third clock phase, said ninth switch being closed during said first and third clock phases, said tenth switch being closed during said second and third clock phases, and said fourteenth switch being closed during said first and second clock phases, said clock phases operating in cyclical fashion with non-overlapping duty times at the same clock frequency.

18 more elements

Dependencies are inferred from the claim text.