Time jitter determining apparatus

Abstract

The jitter determining apparatus uses only a jittery clock signal of period T.sub.b recovered from the received data signal to determine peak to peak jitter J.sub.pp and jitter distribution. The apparatus includes an AND gate having a pair of inputs. The inputs are coupled to a first signal which is the jittery clock signal delayed by a fixed amount nT.sub.b where n is preferably greater than 5, and to a second signal which is a jittery pulse signal generated from the jittery clock signal. The second signal is also controllably delayed by a factor greater than twice the jitter J.sub.pp. The AND gate produces output pulses when coincidence occurs between the two signals as the delay of the second signal is selectively varied. A counter counts the pulses for each selected delay position and thus provides the peak to peak time jitter J.sub.pp of the clock signal.

Dependencies are inferred from the claim text.