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AssigneeInternational Business Machines Corporation
InventorsChristopher H. Bajorek, Dudley A. Chance, Chung W. Ho
Estimating the term…
A chip carrier system for supporting electronic semiconductor chips is provided with a matched coefficient of thermal expansion as well as a high value of capacitance. The carrier provides both mechanical and electrical connections to the chip. A small sized interposer for a silicon chip possesses high capacitance. An array of dot capacitors is formed between laminated layers of ceramic material. In some cases, conductive surfaces are provided on the upper and lower surfaces of a thin film of ceramic material in which dielectric bodies are interspersed in an array of openings therein. The resultant ceramic dielectric combination has a coefficient of thermal expansion which matches the coefficient of thermal expansion of the silicon chip and the substrate thereby relieving stress upon the solder ball joints between the interposer and both the chip and the substrate. This minimizes the mechanical stress upon the solder ball joints during thermal cycling of the structure. Alternatively, an array of multilayer ceramic capacitors has an array of dielectric bodies located within holes in ceramic layers between capacitor plates, or entire arrays of capacitors are formed in the space between ceramic sheets.
In a carrier for electronic circuit chips in which a chip is carried on conductor pads on a first external surface of said carrier which provides mechanical support means and electrical connections through said mechanical support means for said chip, said carrier including a lower surface opposing said first external surface,
In a carrier for electronic circuit chips in which a chip is carried on said carrier which provides mechanical support means and electrical connections through said mechanical support means for said chip the improvement comprising,
On the surface of a carrier for electronic circuit chips with conductor pads thereon is carried a capacitor structure said capacitor structure being constructed of a multilayered ceramic structure of a plurality of ceramic layers laminated together with capacitor plates sandwiched between said ceramic layers, the improvement comprising said capacitor structure being formed by,
A carrier for electronic circuit chips in which a chip is carried upon a chip carrying surface of said carrier,
Dependencies are inferred from the claim text.