Address control system for software simulation
AssigneeFujitsu Limited
InventorsSaburo Kaneda, Takamitsu Tsuchimoto, Kazuyuki Shimizu, Fujio Ikegami
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Abstract
An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.
Claims10
An address control system for software simulation in a data processor, wherein the data processor has a prefix processing unit for producing an absolute address signal, coordinates logical and real addresses of a virtual machine simulated program and a virtual machine monitor simulator program in a main memory, and simulates the execution of a simulated instruction by the execution of at least one of the instructions of the virtual machine monitor simulator program, said system comprising:
- first means for holding information for discriminating the operating state of the virtual machine monitor simulator program and the operating state of the virtual machine simulated program;
- second means, operatively connected to the prefix processing unit, for holding preceding address translation control information and a preceding prefix signal which are both used by the data processor for coordinating a simulated logical operand address with a simulated real operand address in the main memory, when the simulation is performed by the virtual machine monitor simulator program;
- third means, operatively connected to the prefix processing unit, for holding current address translation control information and a current prefix signal which are both used by the data processor for coordinating a simulator logical operand address with a simulator real operand address in the main memory;
- and
- fourth means, operatively connected to said first, said second and said third means, for indicating the selection of the contents of either said second means or said third means as a translation input to the prefix processing unit of the data processor during the operation of the simulator program, the contents of said second means being selected when a simulated operand to be used resides in the virtual machine simulated program, and the contents of said third means being selected when a simulator operand to be used resides in the virtual machine monitor simulator program.
An address control system for software simulation in a data processor, wherein the data processor has a prefix processing unit for producing an absolute address signal, coordinates logical and real addresses of a virtual machine simulated program and a virtual machine monitor simulator program in a main memory, and simulates the execution of a simulated instruction by the execution of at least one of the instructions of the virtual machine monitor simulator program, said system comprising:
- first means for holding information indicating that the data processor has stopped executing the virtual machine simulated program and started executing the virtual machine monitor simulator program;
- second means, operatively connected to the prefix processing unit, for holding preceding address translation control information and a preceding prefix signal which are both used by the data processor for coordinating a simulated logical operand address with a simulated real operand address in the main memory, when the simulation is performed by the virtual machine monitor simulator program;
- third means, operatively connected to the prefix procesing unit, for holding current address translation control information and a current prefix signal which are both used by the data processor for coordinating a simulator logical operand address with a simulator real operand address in the main memory;
- and
- fourth means, operatively connected to said first, said second and said third means, for indicating the selection of the contents of either said second or said third means as a translation input to the prefix processing unit of the data processor during the operation of the simulator program, the contents of said second means being selected when a simulated operand to be used resides in the virtual machine simulator program, and the contents of said third means being selected when a simulated operand to be used resides in the virtual machine monitor simulator program.
Dependencies are inferred from the claim text.