Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus

Serial storage interface apparatus for coupling a serial storage mechanism to an input/output (I/O) bus of a data processor and comprising:

• a first-in-first-out (FIFO) buffer storage mechanism;
• first data transfer circuitry for coupling the FIFO buffer storage mechanism to the data processor I/O bus;
• second data transfer circuitry for coupling the FIFO buffer storage mechanism to the serial storage mechanism;
• bus utilization monitoring circuitry responsive to the data transfer activity of the first data transfer circuitry for generating signals representing values of I/O bus availability;
• and speed control circuitry responsive to the signals representing values of I/O bus availability for causing the serial storage mechanism to operate at different speeds for different values of I/O bus availability to the serial storage interface apparatus.

Serial storage interface apparatus for coupling a serial storage mechanism to an input/output (I/O) bus of a data processor and comprising:

• a first-in-first-out (FIFO) buffer storage mechanism;
• first data transfer circuitry for coupling the FIFO buffer storage mechanism to the data processor I/O bus;
• second data transfer circuitry for coupling the FIFO buffer storage mechanism to the serial storage mechanism;
• FIFO utilization monitoring circuitry coupled to the FIFO buffer storage mechanism and responsive to the amount of data in the FIFO buffer storage mechanism for generating signals representing values of FIFO storage availability;
• and speed control circuitry responsive to the signals representing values of FIFO storage availability for causing the serial storage mechanism to operate at different speeds for different amounts of data in the FIFO buffer storage mechanism.