Power gated decoding

The combination comprising:

• N input variables to be decoded, where N is a positive integer greater than 2;
• first partial decoding means responsive to X of the N input variables for producing Q unique outputs, where X is a positive integer less than N and Q is equal to a maximum of 2.sup.X ;
• second partial decoding means responsive to the remaining N-X inputs for concurrently producing P unique outputs of said remaining N-X inputs, where P is equal to a maximum of 2.sup.N-X ;
• R decoding buffer gates, where R is equal to a maximum of the product of P and Q, each buffer gate having a signal input terminal, first and second power terminals, and an output terminal, each one of said decoding buffer gates being of the type which when the signal at its input terminal is of one binary value and the potential at its first power terminal is of the other binary value produces a signal at its output terminal of said other binary value and which when the signal at its input has said other binary value produces a signal at its output of said one binary value;
• and
• means for producing R unique outputs at the output terminals of said R buffer gates including means for applying each one of said Q outputs to the signal input terminals of P different ones of said R buffer gates and means for applying each one of said P outputs to said first power terminal of Q different ones of said R buffer gates.

The combination comprising:

• N input variables to be decoded, where N is an integer greater than 2;
• decoding means responsive to X of the N inputs variables for producing 2.sup.X unique outputs of the X inputs, where X is an integer which is less than N;
• means responsive to the remaining N-X inputs for simultaneously producing up to 2N-X unique outputs of the remaining N-X inputs;
• 2.sup.N decoding buffer gates each having a signal input terminal, a first power terminal, a second power terminal to which is applied a reference potential, and an output terminal;
• each one of said decoding buffer gates being of the type which when the signal at its input terminal is of one binary value and the potential at its first power terminal is of the other binary value produces a signal at its output terminal of said other binary value, and which when the signal at its input has said other binary value produces a signal at its output of said one binary value;
• and
• means for applying each one of the 2.sup.X outputs to the signal input terminals of 2.sup.N-X different buffer gates;
• and
• means for applying each one of the 2.sup.N-X outputs to the first power terminals of 2.sup.X different buffer gates.

The combination comprising:

• first and second lines;
• N circuits connected between said first and second lines, where N is an integer greater than 1, each of said N circuits having an input terminal and an output terminal, and each of said N circuits including:
• a first insulated-gate field-effect transistor (IGFET) of first conductivity type, and second and third IGFETs of second conductivity type, each IGFET having a conduction path and a control electrode;
• means connecting the conduction path of said first IGFET between said first line and the output terminal of that circuit;
• means connecting the conduction paths of said second and third IGFETs in parallel between the output terminal of that circuit and said second line;
• and means connecting the control electrodes of said first and second IGFETs of each one of said circuits to the input terminal of that circuit;
• means for applying a different first binary signal to each input terminal of said N circuits;
• means for applying a second two-valued binary signal to said first line;
• means for applying a reference potential to said second line;
• and
• means for applying to the control electrode of said third IGFET of each of said N circuits the complement of the signal applied to said first line.

The combination comprising:

• a first insulated-gate field-effect transistor (IGFET) of first conductivity type, and second and third IGFETs of second conductivity type, each IGFET having a conduction path and a control electrode;
• means connecting the conduction path of said first IGFET between a first power terminal and an output terminal;
• means connecting the conduction paths of said second and third IGFETs in parallel between said output terminal and a second power terminal;
• means connecting the control electrodes of said first and second IGFETs to an input terminal;
• means for applying a first two-valued binary signal to said input terminal;
• means for applying a second two-valued binary signal to said first power terminal;
• said first transistor conducting in the source follower mode for one condition of said first and second binary signals and in the common source mode for another condition of said first and second binary signals, said first transistor passing current in one direction when conducting in the source follower mode and in the opposite direction when conducting in the common source mode;
• means for applying a reference potential to said second power terminal;
• and
• means for applying to the control electrode of said third IGFET the complement of the signal applied to said first power terminal, for causing said third transistor to conduct in the common source mode for the signal condition causing said first transistor to conduct in the source follower mode.