Bipolar memory circuit
AssigneeHitachi, Ltd.
InventorsAtsuo Hotta, Yukio Kato, Teruo Isobe
Life of this patent
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Abstract
A bipolar memory circuit is provided with a delay circuit which receives a write enabling signal, a gate circuit which detects the coincidence between an input signal and an output signal of the delay circuit, and a circuit which is started by an output signal of the gate circuit and which provides a pulse signal of a fixed time. The operation of a write driver circuit in the bipolar memory circuit is controlled by the pulse signal. Noise interfering in the write enabling signal are neglected by the use of the delay circuit and the gate circuit. The pulse width of the write enabling signal is permitted to be made smaller than the pulse width of the pulse signal required by the write driver circuit.
Claims8
A bipolar memory circuit comprising:
- a plurality of memory cells,
- an address decoder which receives an address signal and which provides a signal for selecting one of the plurality of memory cells corresponding to the address signal,
- a pulse generator which is started by a write enabling signal and which provides a pulse signal having a fixed pulse duration, and
- a gate circuit which receives an input data signal and the pulse signal and which provides a write pulse signal corresponding to the input data signal to be written into the selected memory cell, for a period determined by said pulse signal.
A bipolar memory circuit comprising:
- a plurality of memory cells,
- an address decoder which receives an address signal and which provides a signal for selecting one of the plurality of memory cells corresponding to the address signal,
- a pulse generator which receives a write enabling signal and which provides a pulse signal corresponding to the write enabling signal,
- a gate circuit which receives an input data signal and the pulse signal and which provides a write pulse signal corresponding to the input data signal to be written into the selected memory cell, for a period determined by said pulse signal,
- an output buffer circuit which receives a signal provided from the selected memory cell and a control signal which provides a signal corresponding to the signal provided from the memory cell, for a period determined by the control signal, and
- a delay circuit which forms an output signal delayed with respect to an input signal thereof,
- an operating timing of said pulse generator and that of said output buffer circuit being made different from each other by said delay circuit.
Dependencies are inferred from the claim text.