Method for the serial transmission of binary data and devices for its implementation

A decoder for receiving a decoder input signal representing a series of binary data digits having first and second values, said series including at least first and second sequences of (n+1) successive binary digits of said second value, said first sequence preceding said second sequence and each of said sequences having first and last digits, m digits of said first value occurring in said series between said first and second sequences, where m is a non-negative integer;

• said decoder input signal comprising a series of first and second elementary signals each having at least one of first and second levels and occupying a time interval known as the binary interval, said first elementary signals having only one of said first and second levels for the duration of said binary interval and said second elementary signals having said first level during the first half of said binary interval and said second level during the second half of said binary interval, said decoder input signal comprising a first elementary signal for each binary digit of said first value, the level of said first elementary signal representing a digit of said first value being different from the level of the most recent preceding first elementary signal in said decoder input signal;
• a second elementary signal for each binary digit of said second value, except said first and last digits;
• a first elementary signal for said first digit in said second sequence when m is an even number, the level of said first elementary signal representing said first digit being different from the level of the most recent first elementary signal and said decoder input signal;
• a second elementary signal for said first digit in said second sequence when m is an odd number;
• and a first elementary signal for said last digit, the level of said first elementary signal representing said last digit being the same as the level of the most recent first elementary signal in said series, said decoder receiving said decoder input signal and providing as a decoder output signal a three-level high density bipolar (HDBn) code, said decoder comprising:
• a clock regeneration circuit receiving said decoder input signal and generating therefrom a clock signal defining said binary intervals, said clock signal having zero-to-one transitions coinciding with those of said decoder input signals;
• a logic AND gate (11) having a first input for receiving said decoder input signal and a second input coupled to the output of said clock regeneration circuit;
• a logic NOR gate (12) having first and second inputs coupled to said first and second inputs, respectively, of said AND gate (11);
• a delay circuit (13) for receiving said clock signal and the output (K) of said NOR gate, said delay circuit delaying said NOR gate output by a half binary interval;
• and
• a differential amplifier (14) having a first input connected to the output of said AND gate (11) and a second input coupled to the output of said delay circuit (13), the output of said differential amplifier comprising the output signal of said decoder.

A regenerator for receiving a signal to be regenerated and providing a regenerator output signal, said signal to be regenerated representing a series of binary data digits having first and second values, said series including at least first and second sequences of (n+1) successive binary digits of said second value, said first sequence preceding said second sequence and each of said sequences having first and last digits, m digits of said first value occurring in said series between said first and second sequences, where m is a non-negative integer, said signal to be regenerated comprising a series of first and second elementary signals each having at least one of first and second levels and occupying a time interval known as the binary interval, said first elementary signals having only one of said first and second levels for the duration of said binary interval and said second elementary signals having said first level during the first half of said binary interval and said second level during the second half of said binary interval, said series of first and second elementary signals comprising a first elementary signal for each binary digit of said first value, the level of each first elementary signal representing a digit of said first value being different from the level of the most recent preceding first elementary signal in said signal to be regenerated;

• a second elementary signal for each binary digit of said second value, except said first and last digits;
• a first elementary signal for said first digit in said second sequence when m is an even number, the level of said first elementary signal representing said first digit being different from the level of the most recent first elementary signal in said signal to be regenerated;
• a second elementary signal for said first digit in said second sequence when m is an odd number;
• and a first elementary signal for said last digit, the level of said first elementary signal representing said last digit being the same as the level of the most recent first elementary signal in said signal to be regenerated, said regenerator comprising:
• a clock regeneration circuit providing at its output (H) a regenerated clock signal defining the binary intervals in said signal to be regenerated;
• a delay circuit (17) connected to said output of said clock regeneration circuit and providing at its output a delayed version of said regenerated clock signal, said delayed version being delayed by a period less than half of the binary interval at a multiple close to the binary interval;
• a first sampling circuit (19) having a first sampling input for receiving the signal to be regenerated, said first sampling circuit having first and second sampling control inputs connected to the outputs (H and H.sub.1) of said clock regeneration circuit and of said delay circuit, said first sampling circuit sampling said signal to be regenerated during a short period (X) in the first half of each binary interval following a transition of said delayed version of the regenerated clock signal;
• a second sampling circuit (20) with a sampling input receiving a complementary version of said signal to be regenerated, said second sampling circuit being connected via sampling control inputs to the outputs (H and H.sub.1) of said clock regeneration circuit and said delay circuit, said second sampling circuit sampling said complementary version of said signal to be regenerated during a short period (Z) in the first and second halves of each binary interval following transitions of said delayed version of said regenerated clock signal;
• and
• a bistable flip-flop (21) having a reset-to-one input connected to the output (P) of said first sampling circuit (19) and a reset-to-zero input connected to the output (0) of said second sampling circuit (20), the output of said bistable flip-flop comprising said regenerator output signal.

An error detector for receiving and detecting errors in a binary digital signal, said binary digital signal representing a series of binary data digits having first and second values, said series including at least first and second sequences of (n+1) successive binary digits of said second value, said first sequence preceding said second sequence and each of said sequences having first and last digits, m digits of said first value occurring in said series between said first and second sequences, where m is a non-negative integer, said binary digital signal comprising a series of first and second elementary signals each having at least one of first and second levels and occupying a time interval known as the binary interval, said first elementary signals having only one of said first and second levels for the duration of said binary interval and said second elementary signals having said first level during the first half of said binary interval and said second level during the second half of said binary interval, said series of first and second elementary signals comprising a first elementary signal for each binary digit of said first value, the level of each first elementary signal representing a digit of said first value being different from the level of the most recent preceding first elementary signal and said binary digital signal;

• a second elementary signal for each binary digit of said second value, except said first and last digits;
• a first elementary signal for said first digit in said second sequence when m is an even number, the level of said first elementary signal representing said first digit being different from the level of the most recent first elementary signal in said binary digital signal;
• a second elementary signal for said first digit in said second sequence when m is an odd number;
• and a first elementary signal for said last digit, the level of said first elementary signal representing said last digit being the same as the level of the most recent first elementary signal in said binary digital signal, said error detector comprising:
• a clock regeneration circuit delivering a regenerated and inverted clock signal (H) defining the binary intervals in said binary digital signal and having trailing edges coincident with the leading edges in said binary digital signal;
• a logic AND gate (39) having a first input receiving said binary digital signal and a second input receiving said regenerated and inverted clock signal;
• a logic NOR gate (40) having first and second inputs coupled to the first and second inputs, respectively, of said AND gate (39);
• a delay circuit (41) receiving the said regenerated and inverted clock signal and the output of said NOR gate (40) and delaying the output of said NOR gate by one-half of a binary interval;
• a frequency doubler (42) receiving and frequency doubling said regenerated and inverted clock signal;
• a bidirectional, four-stage (ABCD) shift-register (43) having a clock input coupled to the output of said frequency doubler, a logic 1 signal level applied to parallel data inputs for stages A and B and to a right-shift serial data input, a logic 0 signal level applied to parallel data inputs for stages C and D and to a left-shift serial data input, a right-shift control input triggered by the output of said AND gate (39), and a left-shift control input triggered by the signal at the output of said delay circuit (41);
• and
• a logic circuit (44) for providing an error signal as the output of said error detector in response to a right or left overflow in said shift-register or in response to two shifts in the same direction within said shift register, said error signal resetting said shift register to its initial state.