Data processing system with self testing and configuration mapping capability

A logic test and configuration map control system in a data processing system including processor means, RAM memory means, and ROM memory means comprising, in combination:

• reader means responsive to said processor means for reading stored data out of the storage locations in said ROM memory means;
• signature means in electrical communication with said reader means for calculating a signature word based on the contents of said stored data;
• and
• means for storing said signature word in a predetermined location in said RAM memory means to form a system configuration map indicative of the operating status and location of said ROM memory means.

A logic test and configuration map control system in a data processing system including processor means, memory means, and a plurality of I/O controller means comprising, in combination:

• means responsive to said processor means for issuing an interrupt request signal to a selected one of said I/O controller means;
• first test means for receiving an interrupt response signal from said selected I/O controller means and for comparing said signal against a predetermined interrupt response value;
• second test means for generating an interrupt status word, including an error flag bit, in response to the result of the comparison performed by said first test means;
• and
• data transfer means for storing said interrupt status word generated by said second test means in a predetermined storage location of said memory means.

A method for operating a logic test and configuration map control system in a data processing system having processing means and memory means, comprising the steps of:

• operating a first test program to determine the functionality of a first section of said memory means;
• inhibiting further operation of said system if said first memory section is determined to function erroneously;
• operating a second test program to determine the functionality of a second section of said memory means;
• and
• storing in said first memory section the results obtained during the operation of said second test program.

A method for operating a logic test and configuration map control system in a data processing system having processor means, RAM memory means, and ROM memory means comprising the steps of:

• sequentially reading stored data out of the storage locations in said ROM memory means;
• calculating a signature word based on the contents of said data read out form said ROM memory means;
• and
• storing said signature word in a predetermined location in said RAM memory means.

A method for operating a logic test and configuration map control system in a data processing system including processor means, memory means, and a plurality of I/O controller means comprising the steps of:

• issuing an interrupt request signal to a selected one of said I/O controller means to test said controller means;
• receiving an interrupt response signal from said selected I/O controller means and comparing said signal against a predetermined interrupt response value;
• generating an interrupt status word, including an error flag bit, in response to the result of the comparison operation performed in said last-mentioned step;
• and
• storing said interrupt status word in a predetermined storage location of said memory means.

A logic self-test and configuration map control system in a data processing system having a processing control means, a system memory means, and plural input/output (I/O) controller means, which comprises:

• (a) self-test memory means in said processor control means for storing firmware instructions to be executed in testing the operability of said processing control means, said system memory means and said plural I/O controller means, and in forming a system configuration table indicative of the operating status and location of each system device tested;
• (b) map memory means in said processing control means and in electrical communication with said self-test memory means and accessible by system devices external to said processing control means for storing said system configuration table;
• (c) microprocessor means in said processing control means and in electrical communication with said self-test memory means and said map memory means for executing said firmware instructions to issue control signals to test said processing control means, said map memory means, said system memory means, and said plural I/O controller means, and to sense responses to said control signals in forming said system configuration table in said map memory means;
• and
• (d) start-up control means in said processing control means and in electrical communication with said microprocessor means for automatically initiating the execution of said firmware instruction by said microprocessor means upon the initiation of a system power-up cycle.