Semiconductor read/write memory array having serial access

A semiconductor memory device fabricated in a single integrated semiconductor circuit, comprising:

• an array of rows and columns of dynamic read/write one-transistor memory cells employing MOS transistors and capacitors, with a bistable sense amplifier circuit for each column for input or output of data,
• a serial register having a plurality of stages, each stage associated with a selected one of said columns;
• transfer means for loading bits of data from the columns into the register stages or from the register stages into the columns in parallel in response to a transfer signal received from external to the device, the transfer means comprising a plurality of transfer gates connected between column lines and said stages;
• means for receiving an address from a source external to the device and for addressing the array for selecting one of the rows for actuation by actuating the gates of all transistors in a row of said cells;
• and
• means for loading a plurality of bits of data serially from said register to utilization means external to the device or from the utilization means to the register whereby a plurality of bits of data is accessed by one address.