US 4,326,332 AGranted

Method of making a high density V-MOS memory array

AssigneeInternational Business Machines Corporation

InventorDonald M. Kenney

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Abstract

A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the thin regions with the use of an etch mask defining a plurality of parallel regions aligned perpendicular to the regions in the masking layer. V-MOSFET devices having self-aligned gate electrodes are formed in the holes and device interconnecting lines are formed under the remaining portions of the thin regions. A combination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of V-grooves. A method of eliminating the overhang of a masking layer after anisotropic etching includes the oxidation of the V-groove followed by etching to remove both the grown oxide and the overhang is also disclosed.

Claims10

Dependent claims

The method of making a matrix of interconnected self-aligned semiconductor devices on the surface of a semiconductor substrate comprising the steps of:

providing an first masking layer on the surface on the surface of a semiconudctor substrate of a first conductivity type, said masking layer having a first plurality of parallel spaced first regions of a first thickness separated by a second plurality of regions of a second thickness greater than said first thickness;
selectively removing a plurality of parallel strip-like regions of said masking layer in a pattern oriented substantially perpendicular to said first regions to expose the surface of said substrate only under those areas of said masking layer common to said first regions and said strip-like regions;
forming a plurality of self-aligned V-MOS semiconductor devices in said exposed areas of said substrate, each of said devices including a gate electrode layer, and then
forming self-aligned conductive means in said substrate to interconnect said MOS semiconductor devices, said conductive means being defined by said first regions in said masking layer and by said gate electrode layers.

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Dependencies are inferred from the claim text.