Programmable sequence controller
AssigneesHitachi, Ltd., Nissan Motor Co., Ltd.
InventorsHiroharu Suda, Keiji Hideshima, Kazuyoshi Asada, Masaoki Takaki, Isao Yasuda, Atsutaro Kamei
Life of this patent
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Abstract
A sequence control system includes a main memory unit for storing therein a sequence program, an operation and control unit for decoding the sequence instruction and executing the designated operations, an input unit for fetching states of a process to be controlled as inputs, and an output unit for producing an output signal to control the process.
Claims7
In a programmable sequence controller which is responsive to the states of a plurality of contacts for controlling one or more output elements, said sequence controller being programmable so as to simulate a circuit formed as a matrix consisting of contacts interconnected in rows, and columns forming branch points between rows of contacts, with said output elements being connected in selected rows of contacts, said matrix including a first voltage node at one marginal column, contacts or output elements between successive ones of said columns, and a second voltage node at the other marginal column, with branch points at selected crosspoints of the rows and the columns at which a signal passing from the first voltage node along the rows is branched along the corresponding column, said programmable sequence controller comprising:
- input selection means for selectively providing on-off state signals indicating the operational state of selected contacts;
- sequence program storage means for storing programmed sequence instructions which simulate said circuit formed as a matrix;
- logical processing means connected to said input selection means and said sequence program storage means for generating an output control signal on the basis of said programmed sequence instructions and said on-off state signals, including
- (1) second storage means for storing an on-off condition signal relating to the on-off condition of a crosspoint at the output of a contact including initially setting the stored value in accordance with the programmed sequence instructions,
- (2) first logical operation means connected to said input selection means and said second storage means for producing said on-off condition signals by a first logical operation between the content of said second storage means and an on-off state signal from said input selection means and for storing the result of said first logical operation in said second storage means as the new content thereof in accordance with the execution of said programmed sequence instructions,
- (3) a plurality of column flip-flops provided in one-to-one correspondence with each of said simulated matrix columns except for said marginal columns thereof for temporarily storing said on-off condition signals for those crosspoints at which there is a branch point in said simulated sequence circuit, and
- (4) second logical operation means connected to said second storage means and said column flip-flops for producing said on-off condition signals by a second logical operation between the content of said second storage means and the on-off condition signal stored in a column flip-flop and for storing the result of said second logical operation in either said second storage means or said column flip-flops or both as new contents thereof in accordance with the execution of said programmed sequence instructions, and
- (5) means for providing the result of the logical operation by said first or second logical operation means as said output control signal;
- and
- output control means connected to said logical processing means for controlling a selected output element on the basis of said output control signal.
In a programmable sequence controller which is responsive to the states of a plurality of contacts for controlling one or more output elements, said sequence controller being programmable so as to simulate a circuit formed as a matrix consisting of contacts interconnected in rows, and columns forming branch points between rows of contacts, with said output elements being connected in selected rows of contacts, said matrix including a first voltage node at one marginal column, contacts or output elements between successive ones of said columns, and a second voltage node at the other marginal column, with branch points at selected crosspoints of the rows and the columns at which a signal passing from the first voltage node along the rows is branched along the corresponding column, said programmable sequence controller comprising;
- input selection means for selectively providing on-off signals indicating the operational state of selected contacts on the basis of an applied address;
- sequence program storage means for storing a plurality of programmed sequence instruction, each instruction including an operation code field and a number field;
- an instruction register connected to said sequence program storage means for storing instructions;
- a decoder responsive to the operation code field of an instruction stored in said instruction register for generating various gate enable signals on selected ones of a plurality of outputs;
- a status flip-flop having an input and an output;
- a plurality of column flip-flops which are individually enabled in response to an applied address;
- output selection means for providing control signals to selected ones of a plurality of output elements on the basis of an applied address;
- means for applying the number field of an instruction stored in said instruction register as said applied address to said input selection means, said plurality of column flip-flops and said output selection means;
- a first AND gate having an input connected to the output of said input selection means and another input connected to the output of said status flip-flop;
- a second AND gate having an input connected to the output of said first AND gate and another input connected to an output of said decoder so as to be enabled by one of said gate enable signals;
- a first OR gate having an input connected to the output of said second AND gate and an output connected to the input of said status flip-flop;
- a third AND gate having an input connected to the outputs of said column flip-flops and another input connected to an output of said decoder so as to be enabled by one of said gate enable signals;
- a second OR gate having an input connected to the output of said third AND gate;
- a fourth AND gate having an input connected to the output of said second OR gate and another input connected to an output of said decoder so as to be enabled by one of said gate enable signals, and having an output connected to another input of said first OR gate;
- a fifth AND gate having an input connected to the output of said status flip-flop and another input connected to an output of said decoder so as to be enabled by one of said gate enable signals, and an output connected to another input of said second OR gate;
- a sixth AND gate having an input connected to the output of said second OR gate and another input connected to an output of said decoder so as to be enabled by one of said gate enable signals, and an output connected to the inputs of said column flip-flops;
- and
- a seventh AND gate having an input connected to the output of said status flip-flop and another input connected to an output of said decoder so as to be enabled by one of said gate enable signals, and an output connected to the input of said output selection means.
Dependencies are inferred from the claim text.