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US 4,325,180 AGranted
Process for monolithic integration of logic, control, and high voltage interface circuitry
AssigneeTexas Instruments Incorporated
InventorPatrick A. Curran
Life of this patent
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Abstract
Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, including various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.
Claims16
A process for the fabrication of a monolithic integrated microelectronic semiconductor circuit including high performance vertical and lateral NPN, P-JFET, P-MOS, and D-MOS components, comprising the steps of:
- (a) selectively forming an n+ region at the surface of a monocrystalline p-type semiconductor substrate, at locations where a vertical NPN, P-JFET, P-MOS, or N-MOS component is to be fabricated;
- (b) epitaxially forming a monocrystalline n-type semiconductor surface layer on said substrate, covering said n+ regions, and locations of said substrate where a D-MOS, or a lateral NPN component is to be fabricated;
- (c) forming p+ regions extending through said epitaxial layer to provide pn junction isolation between components;
- (d) selectively forming a first lightly doped p-type surface region in the isolated portions of said epitaxial layer where P-MOS and N-MOS devices are to be fabricated;
- (e) selectively forming a second lightly doped p-type region in the isolated portion of said epitaxial layer where D-MOS components are to be fabricated;
- (f) selectively forming first, second, third fourth, fifth and sixth medium-doped p-type regions to form the vertical NPN base, the D-MOS backgate contact, the P-JFET and the P-MOS source and drain regions, respectively;
- (g) then selectively forming ten n-type regions to form the vertical NPN collector contact, lateral NPN collector and emitter, N-MOS source and drain, vertical NPN emitter, D-MOS source and drain, P-MOS background contact, and P-JFET gate contact, respectively;
- (h) then selectively forming gate insulators for the JFET, D-MOS, P-MOS and N-MOS components;
- (i) adjusting the P-MOS enhancement threshold voltage;
- (j) selectively implanting boron ions to form depletion channels for P-MOS and P-JFET devices;
- and
- (k) then completing contact vias and metallization.
9 more elements
A process for the monolithic integration of a semiconductor circuit having D-MOS and high performance vertical NPN components, comprising the steps of:
- (a) selectively forming an n+ region at the surface of a monocrystalline p-type semiconductor substrate, at each location where a vertical NPN component is to be fabricated;
- (b) epitaxially forming a monocrystalline n-type surface layer on said substrate, covering each n+ location, and each location where a D-MOS component is to be fabricated;
- (c) forming p+ regions extending through said epitaxial layer to provide pn junction isolation between components;
- (d) selectively forming a lightly-doped p-type region in the isolated portion of said epitaxial layer where D-MOS is to be fabricated.
- (e) selectively forming medium doped p-type regions constituting the vertical npn base and the D-MOS gate contact;
- (f) then selectively forming n-type regions constituting the vertical NPN emitter, the vertical NPN collector contact, and D-MOS source and drain, respectively;
- (g) then selectively forming gate oxide over the D-MOS channel;
- and
- (h) then completing contact vias and metallization.
6 more elements
A process for the monolithic integration of a semiconductor circuit having D-MOS, P-MOS and N-MOS components, comprising the steps of:
- (a) selectively forming an n+ region at the surface of a monocrystalline p-type semiconductor substrate, at locations where a P-MOS or N-MOS component is to be fabricated;
- (b) epitaxially forming a monocrystalline n-type semiconductor surface layer on said substrate, covering said n+ regions, and each location where a D-MOS component is to be fabricated;
- (c) forming p+ regions extending through said epitaxial layer to provide pn junction isolation between components;
- (d) selectively forming a first lightly doped p-type surface region in the isolated portions of said epitaxial layer where P-MOS and N-MOS devices are to be fabricated;
- (e) selectively forming a second lightly doped p-type region in the isolated portion of said epitaxial layer where D-MOS components are to be fabricated;
- (f) selectively forming first, second and third medium-doped p-type regions in said epitaxial layer to form the D-MOS backgate contact, and the P-MOS source and drain, respectively;
- (g) then selectively forming n-type regions to form the N-MOS source and drain, the D-MOS source and drain, and the P-MOS background contact, respectively;
- (h) then selectively forming gate insulators for the D-MOS, P-MOS and N-MOS components;
- (i) adjusting the P-MOS enhancement threshold voltage;
- (j) selectively implanting boron ions to form depletion channels for P-MOS devices;
- and
- (k) then completing contact vias and metallization.
9 more elements
A process for the monolithic integration of a semiconductor circuit having D-MOS, P-MOS, N-MOS and high performance vertical NPN transistor components, comprising the steps of:
- (a) selectively forming an n+ region at the surface of a monocrystalline p-type semiconductor substrate, at locations where an NPN, P-MOS or N-MOS component is to be fabricated;
- (b) epitaxially forming a monocrystalline n-type semiconductor surface layer on said substrate, covering said n+ regions, and each location where a D-MOS component is to be fabricated;
- (c) forming p+ regions extending through said epitaxial layer to provide pn junction isolation between components;
- (d) selectively forming a first p-type surface region in the isolated portions of said epitaxial layer where P-MOS and N-MOS devices are to be fabricated;
- (e) selectively forming a second lightly-doped p-type region in the isolated portion of said epitaxial layer where D-MOS components are to be fabricated;
- (f) selectively forming first, second, third and fourth medium-doped p-type regions to form the NPN base, the D-MOS backgate contact, and the P-MOS source and drain regions, respectively;
- (g) then selectively forming seven n-type regions to form the NPN collector contact and emitter, N-MOS source and drain, D-MOS source and drain, and P-MOS background contact, respectively;
- (h) then selectively forming gate insulators for the D-MOS, P-MOS and N-MOS components;
- (i) adjusting the P-MOS enhancement threshold voltage;
- (j) selectively implanting boron ions to form depletion channels for P-MOS devices;
- and
- (k) then completing contact vias and metallization.
9 more elements
Dependencies are inferred from the claim text.