Self-aligned metal process for integrated injection logic integrated circuits

A method for forming an integrated injection logic integrated circuit having a pattern of narrow dimensioned dielectric regions on a monocrystalline silicon body comprising:

• providing said silicon body;
• forming a first insulating layer on a major surface of said body;
• removing said first insulating layer in areas designated to contain integrated injection logic devices of said integrated circuits;
• forming over said major surface a highly doped polycrystalline silicon layer of conductivity type opposite to that of said body;
• forming openings in said polycrystalline silicon layer by reactive ion etching in the areas designated as the base of the lateral injector transistor of said integrated circuit which results in the structure having substantially horizontal surfaces and substantially vertical surfaces;
• forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces;
• reactive ion etching said second insulating layer to substantially remove the said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body in said areas designated the base of the lateral injector transistor;
• forming said base of the lateral injector transistor;
• annealing the structure to fully form the said base of the said injector transistor, and to drive into the said body the opposite type impurities from said polycrystalline silicon layer and thereby forming the base regions for the vertical transistors of said integrated injection logic integrated circuit;
• forming additional openings in said polycrystalline silicon layer in areas designated as collector regions for said vertical transistors which results in the structure having substantially horizontal surfaces and substantially vertical surfaces;
• forming a third insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces;
• reactive ion etching said third insulating layer to substantially remove said third insulating layer from said horizontal surfaces and to provide additional said narrow dimensioned dielectric regions on said silicon bodies in said areas designated as collector regions for said vertical transistors;
• forming said collector regions of said vertical transistors;
• removing the remaining said polycrystalline silicon layer by etching to leave said pattern of narrow dimensioned on the said major surface;
• and
• forming a conductive layer on said major surface of said body which has portions thereof electrically separated by said narrow dielectric regions for contacting in self-alignment the said base of the lateral transistor, said base and collector regions of said vertical transistor, and said silicon body.