Voltage detection circuit

A voltage detection circuit for detecting whether a voltage to be detected has a high voltage level or a low voltage level comprising:

• a load element group means having a first terminal to which the voltage to be detected is applied, wherein the sum of the threshold voltages of said load element group means is higher than the low voltage level to be detected and lower than the high voltage level to be detected, wherein said load element group means is kept in an off state when the low voltage level is applied thereto and in an on state when the high voltage level is applied thereto;
• a first transistor operatively connected between said second terminal and ground, wherein said load element group means and said first transistor comprise a first inverter;
• and a second inverter, having an output, comprising a series connection of a second transistor and a third transistor, having an input terminal, wherein the voltage to be detected is supplied to the input terminal of said third transistor, said second inverter supplying a low output voltage when the voltage to be detected has a high voltage level and supplying a high voltage output when the voltage to be detected has a low voltage level, so as to control said first inverter, so that the level of the voltage to be detected is estimated by the voltage at a connection point between said second terminal of said load element group and said first transistor.

A voltage detection circuit, operatively connected to a voltage to be detected, a power supply voltage, and to ground, for detecting a high voltage level and a low voltage level, comprising:

• a load element means, having a first terminal operatively connected to the voltage to be detected and having a second terminal, for determining the magnitude of the voltage to be detected, wherein the sum of the threshold voltages of said load element means is greater than the low voltage level to be detected and lower than the high voltage level to be detected;
• a first FET, having a drain operatively connected to said second terminal, having a source operatively connected to ground and having a gate;
• a second FET, having a drain operatively connected to the power supply voltage, having a gate operatively connected to said gate of said first FET at a first node and having a source operatively connected at said first node;
• a third FET, having a gate operatively connected at said first terminal, having a drain operatively connected at said first node and having a source operatively connected to ground;
• a fourth FET, having a drain operatively connected to the power supply voltage, having a gate, and having a source operatively connected to said gate of said fourth FET at a second node;
• a fifth FET, having a drain operatively connected at said second node, having a gate operatively connected at said second terminal and having a source operatively connected to ground,
• wherein said load element means is kept in an off state when the voltage to be detected has a low voltage level, wherein said load element means is kept in an on state when the voltage to be detected has a high voltage level and wherein the level of the voltage to be detected can be approximately determined by the voltage between said second terminal and ground.