US 4,320,881 AGranted

Fail-safe decoder for digital track circuits

AssigneeAmerican Standard Inc.

InventorRichard D. Campbell

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Abstract

A selected unique digital comma-free code word is transmitted through track section rails from one end and, when received at the other end, is applied serially to a shift register which supplies a parallel readout of shifting pattern to one input of a fail-safe comparator. The second comparator input is selected from the different possible digital code patterns of the track code word stored in a memory device. When inputs are equivalent, the comparator passes an input test signal to its output. Absence of comparator output causes the selected stored code word to be stepped through the stored patterns, in reverse order to track code shift, until equivalence is again obtained. The periodic output signals, of approximately 50% duty cycle, are processed through a series filter-rectifier network, tuned to test and periodic output signal frequencies, to energize a track relay to register an unoccupied track section indication.

Claims13

Dependent claims

Track circuit apparatus for a section of railroad track, comprising,

(a) transmitter means coupled to the rails at one end of said section for continuously transmitting through said rails a preselected unique sequential digital track code of selected length to detect the occupancy condition of and to identify said section,
(b) register means coupled to said rails at the other end of said section for sequentially registering the digital code received when the section is unoccupied by a train and continuously producing a parallel output of the existing registered code pattern,
(c) memory means operable for supplying in parallel format a digital code output selected from a plurality of stored digital codes, one for each possible different pattern of said unique track code,
(d) comparator means coupled to said register means and said memory means for comparing the parallel output code patterns,
(e) a test signal source coupled for supplying a test signal input of predetermined characteristics to said comparator means,
(f) said comparator means responsive only to equivalent input code patterns from said register means and memory means for producing a test signal output,
(g) selector means coupled to said memory means and controlled by said comparator means for selecting in a predetermined sequence the stored code pattern output by said memory means when an output test signal is not produced, and
(h) output means coupled to said comparator means and responsive only to periodic output test signals for registering an unoccupied track section indication.

5 more elements

Decoding apparatus for registering the reception of a preselected length, unique, comma-free digital code word transmitted over a communication channel by a transmitter coupled at the remote end of that channel, comprising,

(a) a receiver means coupled to said channel and responsive to the serial reception of the digital code for supplying a parallel digital output having the same number of digits as said preseleced word length,
(b) a read only memory means for supplying a selected output from a stored plurality of parallel digital patterns corresponding to each possible digit pattern of the transmitted comma-free code word,
(c) a comparator means coupled for comparing the outputs of said receiver means and said memory means and responsive only to equivalent digital code patterns for producing an output test signal having preselected characteristics,
(d) a selector means coupled to said memory means and controlled by said comparator means for successively selecting in a predetermined sequence the stored code patterns when a test signal is not produced by said comparator means, and
(e) output means coupled to said comparator means and responsive only to periodic output test signals for registering the reception of correct code words over said channel.

2 more elements

Dependencies are inferred from the claim text.