Method of making high performance bipolar transistor with polysilicon base contacts

A process for fabricating NPN bipolar transistors with a polysilicon base contact being in close-spaced and self-aligned relationship to the emitter contact therefore, comprising the following sequence of steps;

• forming an N.sup.+ -type subcollector region in a P-type silicon substrate;
• forming an N-type epitaxial layer on at least said N.sup.+ -type subcollector;
• forming a layer of P.sup.+ doped polysilicon on at least said N-type epitaxial layer;
• forming a layer of insulating material over said layer of P.sup.+ doped polysilicon;
• etching said layer of insulating material and said polysilicon down to said N-type epitaxial layer to form an opening in said insulating material and said polysilicon;
• forming a thin layer of insulating material on said epitaxial layer at the bottom of said opening and along the sidewalls of said polysilicon layer exposed by said opening while at the same time diffusing the said P.sup.+ doping material from said polysilicon layer into said N-type epitaxial layer to form an extrinsic base region;
• etching by directional reactive ion etching the said thin layer of insulating material at the bottom of said opening as delineated by said sidewalls so as to remove the said insulating material at the bottom of said opening while leaving said insulating material on said sidewalls;
• forming through said opening with insulating sidewalls an intrinsic P-type base region therebelow;
• and
• forming through said opening with insulating sidewalls an N-type region above said P-type intrinsic base region, said N-type region forming a shallow N-type emitter.

A process for fabricating NPN bipolar transistors having a polysilicon base contact in close-spaced and self-aligned relationship to the emitter contact therefor, comprising the following sequence of steps;

• forming an N.sup.+ subcollector region in a P.sup.- silicon substrate;
• forming an N.sup.- epitaxial layer on at least a portion of said N.sup.+ subcollector region;
• forming a layer of P.sup.+ doped polysilicon on at least a portion of said N.sup.- epitaxial layer;
• forming a layer of insulating material over said polysilicon;
• etching said layer of insulating material and polysilicon down to said epitaxial layer to form an opening therethrough;
• thermally forming a thin layer of insulating material on said epitaxial layer at the bottom of said opening and along the sidewalls of said polysilicon layer exposed by said opening to form an insulating material-coated opening while at the same time diffusing the said P.sup.+ doping material from said polysilicon layer into said N.sup.- epitaxial layer to form an extrinsic base region;
• etching by directional reactive ion etching the said thin layer of insulating material at the bottom of said opening as delineated by the sidewalls of said coated opening so as to remove said insulating material at the bottom of said opening while leaving it on said sidewalls;
• forming through said coated opening a first N region therebelow using said coated polysilicon as a mask, said first N region forming a shallow N.sup.+ emitter;
• and
• forming through said coated opening an intrinsic P-type base region beneath said N.sup.+ emitter region using said coated polysilicon as a mask.