US 4,316,284 A · Frame resynchronization circuit for digital receiver

Abstract

Framing of a digital receiver to synchronize with a true framing pattern is realized by employing an autonomous clock to generate framing pattern bits and other timing signal, and by employing a cyclical-redundancy-check (CRC) to eliminate the possibility of framing on false framing patterns. To this end, a frame synchronization circuit detects all possible framing candidate bit positions in a received time division signal and generates a frame resynchronization pulse corresponding to the framing candidate bit positions thereby causing the autonomous clock to synchronize to the associated framing pattern. If the framing pattern on which the clock is synchronized is a false one a loss of CRC signal is generated which initiates synchronizing on the next detected framing pattern. This process is iterated until no loss of CRC signal is generated thereby indicating synchronization on the true framing pattern.

Claims9

Dependent claims

A framing circuit for synchronizing a digital receiver to a received time division multiplexed signal, characterized by,

means responsive to bits of the received time division signal for generating in accordance with a prescribed criterion a code word having a predetermined number of bits,
means for comparing said code word bits with bits of the received time division signal to generate code word error indications,
means for counting a predetermined number of consecutive ones of said code word error indications to generate a resynchronization initiation signal, and
means utilizing said resynchronization initiation signal for determining whether a framing bit pattern the receiver is synchronized with is a false framing bit pattern.

1 more element

A framing circuit for synchronizing a digital receiver to a received time division multiplexed signal, characterized by,

means responsive to bits of the received time division signal for generating in accordance with a prescribed criterion a code word having a predetermined number of bits,
means for comparing said code word bits with bits of the received time division signal to generate code word error indications, and
means utilizing said error indications for determining whether a framing bit pattern the receiver is synchronized with is a false framing bit pattern, said means for determining including means for generating framing bit candidate signals representative of framing bit position candidates in the received time division signal,
means responsive to said code word error indications for generating a resynchronization initiation signal, and
means responsive to said framing bit candidate signals and said resynchronization initiation signal for effecting synchronization of the receiver with a framing bit pattern corresponding to said framing bit candidate signal.

2 more elements

Dependencies are inferred from the claim text.

Frame resynchronization circuit for digital receiver

Life of this patent

Frame resynchronization circuit for digital receiver

Life of this patent

Abstract

Claims9