US 4,316,203 A · Insulated gate field effect transistor

Abstract

An Insulated Gate Field Effect Transistor (IG FET) comprises two depletion mode gate portions formed along the surface of a V-shaped recess in a semiconductor layer, an enhancement mode gate portion disposed between the two depletion mode gate portions, and a source region and a drain region disposed on respective sides of, and adjacent to, the depletion mode gate portion at the surface of the semiconductor layer. The V-shaped recess extends downwardly from the surface of, and through, a first semiconductor layer having comparatively low impurity concentration into an underlying second semiconductor layer having comparatively high impurity concentration. The first semiconductor layer provides, in the recess, the depletion mode gate portion, and the second semiconductor layer provides, in the recess, the enhancement mode gate portion of the IG FET. The source region and drain region are disposed on respective sides of, and adjacent to, the V-shaped recess, and are spaced apart from each other at the uppermost surface of the substrate. The IG FET, as thus described, has a very short effective channel length, but also allows easy formation of electrodes on the source and drain regions. Moreover, the described IG FET is characterized by a high punch-through voltage regardless of the polarity of the voltage applied thereto, and precludes occurrence of the short-channel effect by virtue of the provision of the two depletion mode channels adjacent to the source region and drain region, respectively. A further embodiment employing dual recesses is also disclosed.

Claims12

Dependent claims

An insulated gate field effect transistor, comprising:

a substrate including a first semiconductor layer of a first conductivity type and having a first impurity concentration, said first semiconductor layer having an uppermost surface, and a second semiconductor layer disposed on said surface of said first semiconductor layer and having a second impurity concentration of the same conductivity type as said first impurity concentration, said second semiconductor layer having an uppermost surface, said first impurity concentration being higher than said second impurity concentration,
a source region and a drain region, each of a second conductivity type opposite to said first conductivity type, said source region and said drain region being spaced apart from each other and respectively located at said uppermost surface of said second semiconductor layer,
said substrate having a recess extending downwardly from said uppermost surface of said second semiconductor layer through said second semiconductor layer into and terminating at a point within said first semiconductor layer, said recess separating said source and drain regions and exposing portions of said first and second semiconductor layers,
a gate region extending between said source region and said drain region on said uppermost surface of said second semiconductor layer and on said exposed portions of said first and second semiconductor layers, said gate region comprising first and second depletion mode gate portions located in said second semiconductor layer adjacent to said source region and said drain region, respectively, and an enhancement mode gate portion located in said first semiconductor layer between said first and second depletion mode gate portions and adjacent thereto, said enhancement mode gate portion comprising said terminating point of said recess in said first semiconductor layer.

1 more element

An insulated gate field effect transistor, comprising:

a semiconductor substrate of a first conductivity type,
an epitaxial layer of said first conductivity type disposed on the surface of said substrate, said epitaxial layer comprising (1) a first semiconductor layer of a first impurity concentration of said first conductivity type located on the surface of said semiconductor substrate, and (2) a second semiconductor layer with a second impurity concentration of said first conductivity type disposed on said first layer, said first impurity concentration of said first layer being lower than the impurity concentration of said substrate and higher than said second impurity concentration of said second layer,
a source region and a drain region of a second conductivity type opposite to said first conductivity type, said source region and said drain region being spaced apart from each other and respectively located at the uppermost surface of said second semiconductor layer,
said epitaxial layer having a recess formed therein so as to extend downwardly from said uppermost surface of said second semiconductor layer through said second semiconductor layer into said first semiconductor layer and terminating at a point within said first semiconductor layer, said recess separating said source and drain regions, and
a gate region extending between said source region and said drain region, and comprising first and second depletion mode gate portions and an enhancement mode gate portion, said first depletion mode gate portion and said second depletion mode gate portion being located in said second semiconductor layer and adjacent to said source region and said drain region, respectively, and said enhancement mode gate portion being located in said first semiconductor layer and connected between said first depletion mode gate portion and said second depletion mode gate portion, said terminating point of said recess being comprised in said enhancement mode gate portion, and
a respective conductive contact connected to each said source region and drain region and selectively disposed over the surface of said second semiconductor layer.

3 more elements

An insulated gate field effect transistor, comprising:

a semiconductor substrate of a first conductivity type having an uppermost surface and an impurity concentration corresponding to a first conductivity type,
an insulating film covering said uppermost surface of said semiconductor substrate, said insulating film being discontinuous so as to form an aperture therein,
an epitaxial layer selectively formed on said uppermost surface of said substrate within said aperture, said epitaxial layer comprising (1) a first layer disposed on said uppermost surface of said semiconductor substrate and having said first conductivity type and having an uppermost surface, said first layer having an impurity concentration such that the conductivity of said first layer is lower than the conductivity corresponding to said impurity concentration of said semiconductor substrate, and (2) a second layer of said first conductivity type disposed on said uppermost surface of said first layer and having an uppermost layer, said second layer having an impurity concentration which is lower than said impurity concentration of said first layer, said epitaxial layer having a recess formed therein,
a source region and a drain region, each of a second conductivity type opposite to said first type, said source region and said drain region being spaced apart from each other and located at said uppermost surface of said second layer, said source region and said drain region further extending to said insulating film,
at least one polycrystalline semiconductor layer extending from at least one of said source and drain regions and over said insulating film, each said polycrystalline semiconductor layer being of said second conductivity type, and
a gate region located in said recess in said epitaxial layer within said aperture, said recess extending downwardly from said uppermost surface of said second layer through said second layer into said first layer, said gate region extending between said source region and said drain region and comprising first and second depletion mode gate portions and an enhancement mode gate portion, said first depletion mode gate portion and said second depletion mode gate portion being located within said second layer and adjacent to said source region and said drain region, respectively, and said enhancement mode gate portion being located within said first layer and between said first and second depletion mode gate portions.

3 more elements

An insulated gate field effect transistor, comprising:

a semiconductor substrate of a first conductivity type having an uppermost surface and an impurity concentration corresponding to said first conductivity type, said substrate having a first recess formed in said uppermost surface of said semiconductor substrate extending downwardly from the uppermost surface of said substrate,
an insulating film covering the uppermost surface of said substrate, said insulating film being discontinuous to form an aperture therein so as to expose said first recess,
an epitaxial layer formed selectively over said insulating film and in said first recess of said substrate within said aperture, said epitaxial layer comprising a first layer and a second layer, said first layer being of said first conductivity type, said first layer being located between said substrate and said second layer, said first layer having a respective first impurity concentration corresponding to said first conductivity type, and said second layer having a respective second impurity concentration of said first conductivity type, said first impurity concentration being lower than said impurity concentration of said semiconductor substrate and higher than said second impurity concentration,
a source region and a drain region of a second conductivity type opposite to said first conductivity type, said source region and said drain region being spaced apart from each other and located at the uppermost surface of said second layer, said source region and said drain region further extending to said insulating film,
a polycrystalline semiconductor layer extending from at least one of said source and drain regions over said insulating film, said polycrystalline layer being of said second conductivity type, and
said epitaxial layer having a second recess located directly above said first recess and extending downwardly from said uppermost surface of said second layer through said second layer into said first layer, said gate region extending between said source region and said drain region and comprising first and second depletion mode gate portions and an enhancement mode gate portion, said first depletion mode gate portion and said second depletion mode gate portion being located on said second layer within said second recess and adjacent to said source region and said drain region, respectively, and said enhancement mode gate portion being located on said first layer and connected between said first and second depletion mode gate portions.

3 more elements

Dependencies are inferred from the claim text.

Insulated gate field effect transistor

Life of this patent

Insulated gate field effect transistor

Life of this patent

Abstract

Claims12