Processing element for parallel array processors
AssigneeGoodyear Aerospace Corporation
InventorKenneth E. Batcher
Life of this patent
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Abstract
A processing element constituting the basic building block of a massively-parallel processor. Fundamentally, the processing element includes an arithmetic sub-unit comprising registers for operands, a sum-bit register, a carry-bit register, a shift register of selectively variable length, and a full adder. A logic network is included with each processing element for performing the basic Boolean logic functions between two bits of data. There is also included a multiplexer for intercommunicating with neighboring processing elements and a register for receiving data from and transferring data to neighboring processing elements. Each such processing element includes its own random access memory which communicates with the arithmetic sub-unit and the logic network of the processing element.
Claims15
A matrix of a plurality of processing elements interconnected with each other and wherein each processing element comprises:
- a memory;
- an adder;
- a selectably variable length shift register operatively connected to said adder, said shift register comprising a plurality of individual shift registers having gates interposed therebetween, said gates selectively interconnecting said individual shift registers;
- and
- communication means connected to neighboring processing elements within said matrix and further connected to said adder and memory for transferring data between said memory, adder, and neighboring processing elements.
An array of a plurality of processing elements interconnected with each other and wherein each processing element comprises:
- an adder;
- first and second data registers connected with and supplying data bits to said adder;
- a carry register connected to said adder and receiving therefrom data bits resulting from arithmetic operations and which functions according to the rule:
- C.rarw.APvPCvAC where A is the state of said first register, P is the state of said second register, and C is the state of said carry register;
- a memory;
- and
- a data bus interconnecting said first, second, and carry registers and said memory for the transfer of data thereamong.
Dependencies are inferred from the claim text.