Method of manufacturing submicron channel transistors
AssigneeRCA Corporation
InventorSheng T. Hsu
Life of this patent
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Abstract
A short channel insulated gate field effect transistor, suitable for use in high speed integrated circuits is described as being manufactured by a self-aligned process in which the gate electrode is formed by a selective etching technique. In practicing the process, an etch limiting element is laterally diffused from an adjacent solid source into a polycrystalline silicon layer. In one embodiment, a portion of the solid source serves as a mask in another step of the process to define the length of a drain extension region.
Claims11
An improved method of making a semiconductor device which includes forming a low resistivity conductive line from a layer of semiconductor material insulated from the surface of a semiconductor body of a given conductivity type, the line having a substantially submicron width produced by introducing an etch limiting element into the wider layer of semiconductive material by lateral diffusion to define a narrower doped region in the wider layer and then subjecting the wider layer to a selective etching solution to remove the undoped material of the wider layer to the exclusion of the doped material of the doped region, the improvement comprising:
- depositing a first layer of insulating material on the surface of the semiconductor body;
- forming a solid source of the etch limiting element on a portion of the surface of the first insulating layer;
- depositing a second layer of insulating material on the solid source;
- removing a portion of the solid source and first and second layers of insulating material from the surface of the semiconductor body to define and expose an edge on the solid source adjacent the desired location of one edge of the strip-shaped layer;
- growing a gate insulating layer on the surface of the semiconductor body not covered by the solid source;
- depositing the wider layer of the semiconductor material on the surface of the third insulating layer with a portion thereof in lateral contact with the exposed edge of the solid source;
- and
- heating the device to laterally diffuse the etch limiting element out of the solid source and into the wider layer at a given temperature and for a time sufficient to extend the doped region to a predetermined, relatively short distance from the edge of the solid source.
Dependencies are inferred from the claim text.