Parallel processor having central processor memory extension

In a digital data processing system including a CPU and a main memory consisting of a first memory portion and a second memory portion, a parallel processor, first bus means for connecting said parallel processor between said CPU and said first memory portion, said parallel processor comprising:

• comprising means for permitting to connect said second memory portion to said first memory portion;
• first means for transferring data over said first bus means from said first memory portion to said second memory portion for storage therein;
• means for arithmetically manipulating said data stored in said second memory portion to achieve arithmetically manipulated data;
• second bus means connected between said manipulating means and said second memory portion for transferring said data stored in said second memory portion to said manipulating means and for transferring said arithmetically manipulated data to said second memory portion;
• and
• said first transferring means including other means for transferring certain of said arithmetically manipulated data over said first bus means and from said second memory portion to said first memory portion for storage therein, whereby said CPU may operate on data stored data in said first memory portion without interference from said arithmetic manipulating means and whereby said arithmetic manipulating means may operate on data stored in said second memory portion without competing intereference from said CPU, said CPU and arithmetic manipulating means operating on said main memory in parallel.