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US 4,309,762 AGranted
Semiconductor memory apparatus
AssigneeFujitsu Limited
InventorKazuhiro Toyoda
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus is formed of a plurality of memory cells, each of which is connected to a first word line and a second word line. According to the present invention, emitters of the transistors by which the hold current of the memory cells are determined have different areas, so that the hold currents which are supplied to each of said memory cells are uniformly distributed.
Claims8
A semiconductor memory apparatus, having memory cells which are connected to first and second word lines, comprising:
- first and second transistors, included in each of the memory cells, for supplying a hold current, each of said first and second transistors having an emitter region which determines said hold current, and said first and second transistors of each of the memory cells having emitter regions which have an area different from the area of the emitter regions of the first and second transistors of the other memory cells so that the hold currents of the memory cells are uniformly distributed.
A semiconductor memory apparatus, having groups of memory cells which are connected to first and second word lines, comprising:
- first and second transistors, included in each of the memory cells, for supplying a hold current,
- wherein an emitter region in each of said first and second transistors determine said hold current, and wherein said first and second transistors of a first group of the memory cells have emitter regions which have a different area from the emitter regions of the first and second transistors of a second group of the memory cells so that the hold currents of the memory cells are uniformly distributed.
A semiconductor memory apparatus, having first and second word lines comprising:
- a first memory cell operatively connected to said first and second word lines, comprising:
- a first transistor pair, operatively connected to said first and second word lines, for supplying a first hold current, wherein each of the transistors of said first transistor pair has an emitter region, and wherein the emitter regions of the transistors of said first transistor pair determine said first hold current;
- a second memory cell, operatively connected to said first and second word lines, comprising:
- a second of pair of transistors, operatively connected to said first and second word lines, for supplying a second hold current, wherein each of the transistors of said second transistor pair has an emitter region, and wherein the emitter regions of the transistors of said second transistor pair determine said second hold current;
- wherein the transistors of said first transistor pair have emitter regions which have a different area from the emitter regions of the transistors of said second transistor pair, whereby the hold currents of said first and second memory cells are uniformly distributed.
2 more elements
A semiconductor memory apparatus, having memory cells which are connected to first and second word lines, comprising:
- first and second transistors, included in each of the memory cells, for supplying a hold current, each of said first and second transistors having an emitter region which determines said hold current, and said first and second transistors of each of the memory cells having emitter regions which have an area different from the area of the emitter regions of the first and second transistors of the other memory cells so that the hold currents of the memory cells are uniformly distributed, each of the memory cells further comprising:
- first and second resistors operatively connected to the first word line, said first and second transistors each having a collector operatively connected to said first and second resistors, respectively, said first and second transistors each having an emitter which is commonly connected to the second word line, said first transistor having a base which is connected to the collector of said second transistor, and said second transistor having a base which is connected to the collector of said first transistor.
A semiconductor memory apparatus, having memory cells which are connected to first and second word lines, comprising:
- first and second transistors, included in each of the memory cells, for supplying a hold current, each of said first and second transistors having an emitter region which determines said hold current, and said first and second transistors of each of the memory cells having emitter regions which have an area different from the area of the emitter regions of the first and second transistors of the other memory cells so that the hold currents of the memory cells are uniformly distributed, each of the memory cells being formed by integrated injection logic and comprising said first and second transistors, wherein said first and second transistors are of a first conductivity type and have a common emitter forming an injector connected to the first word line, and third and fourth transistors of a second conductivity type each of which has a collector connected to a collector of said first and second transistors, said third transistor having a base which is connected to said collector of said fourth transistor, said fourth transistor having a base which is connected to said collector of said third transistor, and said first and second transistors having bases which are connected to the emitter of said third and fourth transistors and to the second word line.
Dependencies are inferred from the claim text.