Step-oriented pipeline data processing system
AssigneeCalifornia Institute of Technology
InventorKenneth R. Castleman
Life of this patent
Estimating the term…
Abstract
Architecture for step-oriented pipeline data processing is disclosed utilizing a plurality of cascaded modules, each module including a programmable general purpose processor and a read/write random access memory. The memory of each module, shared with the next module in cascade serves as an output memory for the processor and the input memory for the next processor. An additional memory is provided to serve as the input memory of the first module, and each module is provided with a memory, which may be a read-out memory, to store a program for the processor. Each module is further provided with a logic network for resolving a potential memory sharing conflict by awarding priority to the processor of the module.
Claims8
An architecture of a step-oriented pipeline data processing system comprised of cascaded computing modules, each module including a programmable general purpose processor, a memory for storing a program for the processor, and a general purpose read/write memory, where the memory of each successive module in cascade is shared with the processor of the next module to serve as an output memory for one processor and the input memory for the next processor.
The combination of at least two computing modules, said modules being coupled to each other in cascade, wherein each computing module comprises
- a general purpose processor for processing data in accordance with stored program instructions,
- a first memory coupled electronically to said processor, said first memory containing a plurality of stored program instructions controlling said microprocessor, and
- a second two-port read/write memory coupled electronically through one port to said processor and coupled electronically through the other port to a processor of the next module in cascade, said second memory providing storage for output data through said one port for said processor, and providing a source of data for the microprocessor of the next module through said other port.
A data processing system comprising a plurality of programmed processors and a plurality of read/write memories for step-oriented pipeline data processing each memory for storing the output of one programmed processor for access by another processor in sequence and each programmed processor including a second memory for storing its program, each microprocessor being coupled to one other read/write memory in cascade through a unique interface network having two ports for access thereto by the two processors for sequential step-oriented pipeline, and means for resolving a potential memory-sharing conflict between processors arising when two processors address a shared memory for access thereto at the same time comprising
- means for producing first and second select signals in response to a first and a second of the two processors addressing said memory through said first and second ports, respectively,
- means responsive to said select signals for determining which of said ports connected to said shared memory is to have access to said memory.
Dependencies are inferred from the claim text.