Circuit for rapidly resynchronizing a clock
AssigneeTelecommunications Radioelectriques et Telephoniques T.R.T.
InventorJean-Pierre Baudoux
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Abstract
A circuit for rapidly resynchronizing a clock with an external clock is disclosed. The clock to be synchronized is obtained at the output of a phase-locked loop by dividing the frequency of a reference clock in a frequency divider whose division factor is controlled by a phase controller which detects the deviation between the transitions of the two clocks to be synchronized. According to the invention, the pulses of the reference clock are applied to the phase-locked loop by means of a gate, with this gate being rendered nonconductive by means of the characteristic transition of the clock to be synchronized which follows the appearance of a resynchronizing control signal, and thereafter this gate is rendered conductive by means of a characteristic transition of the external clock.
Claims2
A circuit for rapidly resynchronizing a clock with an external clock, the generator of the clock to be synchronized comprising a phase-locked loop supplying the desired clock signal by dividing the frequency of a reference clock signal in a frequency divider, the division factor of which is controlled by a phase comparator which detects the deviation between the characteristic transitions of the two clock signals to be synchronized, characterized in that the reference clock pulses are applied to the phase-locked loop by a gate, and that means are provided for rendering this gate nonconductive by the characteristic transition of the clock to be synchronized which follows the appearance of a resynchronizing control signal, and for thereafter rendering this gate conductive by a characteristic transition of the external clock.
Dependencies are inferred from the claim text.