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US 4,308,596 AGranted
Memory driving method
AssigneeHitachi, Ltd.
InventorsAtsushi Takai, Yuzo Kita, Yoshimune Hagiwara, Terumi Sawase, Takaaki Hagiwara
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AssigneeHitachi, Ltd.
InventorsAtsushi Takai, Yuzo Kita, Yoshimune Hagiwara, Terumi Sawase, Takaaki Hagiwara
Estimating the term…
In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference V.sub.p exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference V.sub.p exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference V.sub.p exists between the substrate and the gate and when a potential difference V.sub.wd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage V.sub.wd between the source and drain and the substrate of the cell, applying a voltage V.sub.p between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.
A memory driving method for erasing the contents of some selected memory cells in an array of memory cells each of which has at least a gate electrode, a substrate and source and drain electrodes, said method comprising a first step of applying a first predetermined voltage to at least one of the source and drain electrodes of each of only those non-selected memory cells not to be erased, and a second step of applying a second predetermined voltage between the gate electrodes and the substrates of only said non-selected memory cells during the application of said first voltage, whereby the contents of said non-selected memory cells are prevented from erroneously changing.
A memory driving method for erasing the contents of some selected memory cells in an array of memory cells each of which has at least a gate electrode, a substrate, and source and drain electrodes, said method comprising a first step of applying a first predetermined voltage to at least one of the source and drain electrodes of each of only those non-selected memory cells not to be erased when an erasing operation signal rises up, a second step of applying a second predetermined voltage to the gate electrodes of said non-selected memory cells during the application of said first voltage, and a third step of applying a third voltage substantially equal to said second voltage to the substrates of said non-selected memory cells during the application of said second voltage, whereby the contents of said non-selected memory cells are prevented from erroneously changing at the beginning of the erasing operation.
A memory driving method for driving a plurality of memory cells each of which has gate, source and drain electrodes and a substrate and in each of which information is stored when a first predetermined voltage is applied between the gate electrode and the substrate and the stored information is not changed when a second predetermined voltage is applied to at least one of the source and drain electrode and said first voltage is applied between the gate electrode and the substrate, said method comprising, in at least one of the beginning and end of an operation of erasing selected memory cells:
A memory driving method for driving a plurality of memory cells each of which has gate, source and drain electrodes and a substrate and in each of which information is stored when a first predetermined voltage is applied between the gate electrode and the substrate and the stored information is not changed when a second predetermined voltage is applied to at least one of the source and drain electrode and said first voltage is applied between the gate electrode and the substrate, said method comprising:
Dependencies are inferred from the claim text.