Back to results
US 4,308,589 AGranted
Apparatus for performing the scientific add instruction
AssigneeHoneywell Information Systems Inc.
InventorsThomas F. Joyce, Richard A. LeMay, William E. Woods, Richard P. Brown
Life of this patent
Estimating the term…
Abstract
The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.
Claims14
A processor comprising:
- a first and a second random access memory, each storing mantissas of a first and a second operand for performing a scientific ADD instruction;
- a third and a fourth random access memory, each storing exponents of said first and said second operands for performing said scientific ADD instruction;
- a first arithmetic logic unit coupled to said third and fourth random access memories for receiving said exponent of said first operand from said third random accesss memory, and said exponent of said second operand from said fourth random access memory, and generating a first signal in a first state if said exponent of said first operand is smaller than said exponent of said second operand, and generating said first signal in a second state, if said exponent of said first operand is equal to or larger than said exponent of said second operand, said first arithmetic unit further generating a first plurality of shifter signals indicating the difference in value between the exponents of said first and second operands;
- a second arithmetic logic unit coupled to said third and fourth random access memories for receiving said exponent of said first operand from said third random access memory, and said exponent of said second operand from said fourth random access memory, and generating a second signal in a first state if said exponent of said first operand is equal to or larger than said exponent of said second operand, and generating said second signal in a second state, if said exponent of said first operand is smaller than said exponent of said second operand, said second arithmetic unit further generating a second plurality of shift signals indicating the difference in value between the exponents of said first and second operands;
- first multiplexing means coupled to said first and second arithmetic logic units and responsive to said second signal in said first state for selecting said first plurality of signals, and responsive to said second signal in said second state for selecting said second plurality of signals;
- address selection means coupled to said first, second, third and fourth random access memories for reading out said exponent of said first operand from said third random access memory and said exponent of said second operand from said fourth random access memory, said address selection means being responsive to said first signal in said first state for reading out said mantissa of said first operand from said second random access memory and said mantissa of said second operand from said first random access memory, and responsive to said first signal in said second state for reading out said mantissa of said first operand from said first random access memory and reading out said mantissa of said second operand from said second random access memory;
- shifting means coupled to said second random access memory and to said multiplexer means for receiving said mantissa of said first operand to be shifted an amount indicated by said first plurality of shift signals when said exponent of said first operand is smaller than said exponent of said second operand, and receiving said mantissa of said second operand to be shifted an amount indicated by said second plurality of shift signals when said exponent of said second operand is smaller than said exponent of said first operand;
- and
- a third arithmetic logic unit coupled to said shifter means and said first random access memory, for receiving said mantissa of said first operand from said first random access memory, and said mantissa of said second operand shifted by an amount indicated by said second plurality of shift signals, or receiving said mantissa of said second operand from said first random access memory, and said mantissa of said first operand shifted by an amount indicated by said first plurality of shift signals, for generating a result.
6 more elements
A processor for performing scientific arithmetic comprising:
- random access memory means including a first and a second random access memory, each storing a first and a second mantissa;
- a third and a fourth random access memory, each storing a first and a second exponent;
- first arithmetic logic unit means coupled to said random access memory means for indicating a smaller of said first and second exponents and the difference between said first and said second exponents;
- address selection means coupled to said first arithmetic logic unit means and said random access memory means for selecting said first mantissa if said first exponent is smaller than said second exponent and selecting said second mantissa if said second exponent is smaller than said first exponent;
- shifting means coupled to said arithmetic logic unit and to said random access memory for receiving and shifting said first or said second mantissa corresponding to the smaller of said first or said second exponents by said amount that said first and said second exponents differ;
- second arithmetic logic means coupled to said random access memory means and to said shifting means for receiving said first or said second mantissa corresponding to a larger of said first or said second exponents from said random access memory or for receiving said first mantissa from said random access memory if said first and said second exponents are equal, and receiving said first or said second mantissa having said smaller of said first or said second exponents shifted by said amount that said first and said second exponents differ, from said shifting means, or receiving said second mantissa from said shifting means if said first exponent equals said second exponent, said second arithmetic logic means receiving said first and said second mantissas and performing said scientific ADD instruction in one processor cycle.
3 more elements
Dependencies are inferred from the claim text.