Binary to one of N decoder having a true and a complement output
AssigneeMotorola, Inc.
InventorPhilip S. Smith
Life of this patent
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Abstract
A digital decoder for use with a dual bus system is provided having a minimum number of transistors. The decoder is easily expandable to decode larger binary coded input signals. As a minimum only six transistors are needed to decode a three-bit binary input signal to provide outputs for a data bus and its complement. By using a minimum number of transistors, less current is required for the decoder. The circuitry used to provide each decoded output is repeated in a manner which conserves silicon area when the decoder is placed on silicon. A minimum number of control lines are used.
Claims10
A digital decoder useful in a digital system requiring a true and a complement output, comprising:
- a plurality of decoding circuits, wherein the number of decoding circuits is equal to 2.sup.n where n is the number of input bits to be decoded, the decoding circuits having a first, a second, and a third transistor all coupled in series between a first output and a voltage terminal wherein the first transistor is connected to the first output and the third transistor is connected to the voltage terminal, the first transistor being controlled by a first input signal, the second transistor being controlled by a second input signal, and the third transistor being controlled by a third input signal, a fourth transistor coupled from the voltage terminal to a second output and being controlled by the second input signal, a fifth transistor coupled from the voltage terminal to the second output, the fifth transistor being controlled by the first input signal, and a sixth transistor coupled from the second output and the voltage terminal and being controlled by the third input signal.
A digital decoder capable of decoding a binary coded signal having at least three bits and capable of selecting one of a plurality of outputs depending on information contained in the binary coded signal, the selected output will have a true and a complement output, comprising:
- (a) a first transistor coupled to a true output and being controlled by a first bit of the at least three bits,
- (b) at least a second transistor coupled in series with the first transistor and being controlled by a second bit of the at least three bits,
- (c) a third transistor coupled to the at least second transistor and coupled to a reference potential and being controlled by a third bit of the at least three bits,
- (d) a fourth transistor coupled from the complement output to the reference potential and being controlled by the first bit,
- (e) a fifth transistor coupled from the complement output to the reference potential and being controlled by the second bit,
- (f) a sixth transistor coupled between the complement output and the reference output and being controlled by the third bit,
- (g) elements set out in (a) through (f) above being repeated 2.sup.n times where n equals the number of bits in the binary coded signal.
Dependencies are inferred from the claim text.