Vital rate decoder

Abstract

A vital rate decoder for actuating one of a plurality of output relays in correspondence with the frequency of an input signal applied thereto, comprising a main rate decoding processor for evaluating the frequency and duty cycle of the input signal by establishing permissible rate windows defined by predetermined tolerances such that the output device corresponding to a frequency can be actuated only when the input signal has a rate code falling in a respective rate window with a predetermined duty cycle tolerance. The rate decoding processor produces plural checkwords having predetermined values based on failure-free rate decoding of the input signal. The checkwords are processed by a checking processor which produces a relay actuating signal only if valid checkwords are produced. The checking processor uses the checkwords to select and load predetermined bytes into a pair of vital counting registers which are then successively decremented. The checking processor then compares the decremented counter register contents at each step to verify that the contents thereof bear a predetermined relationship such that the output device corresponding to the rate code of the input signal is actuated only until the counting registers reach a predetermined count and only so long as the comparison of the contents of the pair of counting registers bear the predetermined relationship.

Dependencies are inferred from the claim text.