Method and a circuit arrangement for expanding the addressing capacity of a central unit, in particular of a microprocessor

A circuit arrangement for extending the addressing capacity of a central unit beyond the multi-base address capacity defined by the address stock of an instruction counter, said central unit operable to emit base addresses and instructions related to operations to be carried out, said circuit arrangement comprising:

• an address bus connected to the central unit for carrying base addresses;
• an outgoing address bus;
• fixed word memory means, comprising a plurality of fixed word memories, operable to produce a plurality of data words;
• a program instruction line connected to the central unit for carrying a program instruction control signal;
• a comparator connected to said address bus, to said fixed word memory means and to said program instruction line and operable to produce an output signal in response to a match between a base address and a data word during the presence of said program instruction control signal;
• and
• extension memory means connected between said address bus and said outgoing address bus and connected to said comparator, said extension memory means including a plurality of memories each storing a different number of additional address bits and operable in response to said output signal to switch through the base address and combine therewith the stored additional bits to form an extension address on said outgoing address bus,
• said comparator including a plurality of outputs associated with respective fixed word memories for carrying said output signal and connected to respective extension memories to associate the extension and fixed word memories.