Programmable controller

An improved programmable controller of the type having a central processing unit (CPU), an addressable memory having more than 1.5.times.N addressable memory locations, each memory location capable of storing P data bits, where P is an integer greater than one, an input/output (I/O) system, a bus interconnecting the CPU, memory and I/O, and wherein the programmable controller is able to store user logic defining a control program for execution by the programmable controller wherein the user logic may comprise up to N possible nodes, where N is a positive integer, wherein the improvement comprises:

• (A) first means, interconnected to the bus and forming part of the memory, for storing up to N data words representing the user nodes, each data word comprising up to 1.5.times.P bits of data so that for each data word "i", where i=1, . . . , N, up to P data bits are stored in memory location "j" of the addressable memory, where J=base address (base addR)+i-1, and so that the remaining data bits of the data word "i", if any, are stored in up to half the memory space of memory location "k" of the addressable memory, where K=(j/2)+"widget", where "widget"=((base addR)/2)+N, and where the remainder of j/2 determines which half of addressable memory location"k" to use to store the remaining data bits of data word "i", and
• (B) second means, interconnected to the bus and forming part of the memory, for reading the data words from the addressable memory so that for any data word "i" data is read from addressable memory location "j" and combined with the data bits corresponding to data word "i" stored in addressable memory location "k", wherein this means further increases the length of data word "i" to equal 1.5.times.P bits, when the data word "i" has less than 1.5.times.P significant data bits, by further combining non-data significant bits to the data significant bits read from addressable memory locations "j" and "k" so as to equal 1.5.times.P bits;
• whereby all data words N are stored and packed in the addressable memory in the same manner regardless of the number of data bits in any given data word, and wherein these data words are stored in the addressable memory beginning at an address defined by the base address so that a flexible address boundary is realized between the addressable memory locations for non-user node storage and that utilized for user logic node storage.